
W90P710CD/W90P710CDG
Publication Release Date: September 19, 2006
- 219 - Revision B2
Continued.
BITS DESCRIPTIONS
[15:12] EPB_ALT Endpoint B alternative setting (READ ONLY)
[11:8] EPB_INF Endpoint B interface
[7:4] EPB_CFG Endpoint B configuration
[3:0] EPB_NUM Endpoint B number
USB Endpoint B Control Register (EPB_CTL)
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
EPB_CTL 0xFFF06068 R/W USB endpoint B control register 0x0000_0000
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
Reserved EPB_ZERO EPB_STL_CLR EPB_THRE EPB_STL EPB_RDY EPB_RST EPB_EN
BITS DESCRIPTIONS
[31:7] Reserved
[6] EPB_ZERO Send zero length packet back to HOST
[5] EPB_STL_CLR Clear the Endpoint B stall(WRITE ONLY)
[4] EPB_THRE
Endpoint B threshold (only for ISO)
1: once available space in FIFO over 16 bytes, DMA
accesses memory
0: once available space in FIFO over 32 bytes, DMA
accesses memory
[3] EPB_STL Set the Endpoint B stall
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