Rainbow-electronics ATA6824 Manual de usuario descargar pdf (Pagina 8)

4931C–AUTO–09/06

ATA6824 [Preliminary]

If triggering fails, /RESET will be pulled to ground for a shortened reset time of typically 2 ms.

The watchdog start sequence is similar to the power-on reset.

The internal oscillator is trimmed to a tolerance of < ±10%. This means that t

and t

can also

vary by ±10%. The following calculation shows the worst case calculation of the watchdog

period T

which the microcontroller has to provide.

1min

= 0.90 × t

= 10.87 ms, t

1max

= 1.10 × t

= 13.28 ms

2min

= 0.90 × t

= 8.65ms, t

2max

= 1.10 × t

= 10.57 ms

wdmax

= t

1min

+ t

2min

= 10.87 ms + 8.65 ms = 19.52 ms

wdmin

= t

1max

= 13.28 ms

= 16.42 ms ±3.15 ms (±19.1%)

Figure 5-2 on page 7 shows the typical watchdog period T

depending on the value of the

external resistor R

OSC

A reset will be active for V

< V

tHRESx

; the level V

tHRESx

is realized with a hysteresis (HYS

RESth

5.4 High Voltage Serial Interface

A bi-directional bus interface is implemented for data transfer between hostcontroller and the

local microcontroller (SIO).

The transceiver consists of a low side driver (1.2V at 40 mA) with slew rate control, wave shap-

ing, current limitation, and a high-voltage comparator followed by a debouncing unit in the

receiver.

5.4.1 Transmit Mode

During transmission, the data at the pin TX will be transferred to the bus driver to generate a bus

signal on pin SIO.

To minimize the electromagnetic emission of the bus line, the bus driver has an integrated slew

rate control and wave-shaping unit. Transmission will be interrupted in the following cases:

• Thermal shutdown active or overtemperature SIO active

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