Rainbow-electronics AT40K40LV Manual de usuario

1Features• Ultra High Performance– System Speeds to 100 MHz– Array Multipliers > 50 MHz– 10nsFlexibleSRAM– Internal Tri-state Capability in Each Ce

10AT40K/AT40KLV Series FPGA0896C–FPGA–04/02Figure 6. Some Single Cell ModesLUTLUTLUTLUT LUT2:1 MUX LUTLUTDQDQQQ (Registered)DQDQSynthesis Mode. This m

11AT40K/AT40KLV Series FPGA0896C–FPGA–04/02RAM 32 x 4 dual-ported RAM blocks are dispersed throughout the array, see Figure 7. A 4-bitInput Data Bus c

12AT40K/AT40KLV Series FPGA0896C–FPGA–04/02Reading and writing of the 10 ns 32 x 4 dual-port FreeRAM are independent of eachother. Reading the 32 x 4

13AT40K/AT40KLV Series FPGA0896C–FPGA–04/02Figure 9. RAM Example: 128 x 8 Dual-ported RAM (Asynchronous)2-to-4 DecoderDout(4)Dout(5)Dout(6)Dout(7)Din

14AT40K/AT40KLV Series FPGA0896C–FPGA–04/02Clocking Scheme There are eight Global Clock buses (GCK1 - GCK8) on the AT40K/AT40KLV FPGA.Each of the eigh

15AT40K/AT40KLV Series FPGA0896C–FPGA–04/02Figure 10. Clocking (for One Column of Cells)Global Clock Line(Buried)Sector Clock MuxColumn Clock MuxSecto

16AT40K/AT40KLV Series FPGA0896C–FPGA–04/02Set/Reset Scheme The AT40K/AT40KLV family reset scheme is essentially the same as the clock schemeexcept th

17AT40K/AT40KLV Series FPGA0896C–FPGA–04/02Figure 11. Set/Reset (for One Column of Cells)Each Cell has a Programmable Set or ResetGlobal Set/Reset Lin

18AT40K/AT40KLV Series FPGA0896C–FPGA–04/02I/O StructurePAD The I/O pad is the one that connects the I/O to the outside world. Note that not all I/Osh

19AT40K/AT40KLV Series FPGA0896C–FPGA–04/02Primary, Secondary andCorner I/OsThe AT40K/AT40KLV has three kinds of I/Os: Primary I/O, Secondary I/O and

2AT40K/AT40KLV Series FPGA0896C–FPGA–04/02Note: 1. Packages with FCK will have 8 less registers.Description The AT40K/AT40KLV is a family of fully PCI

20AT40K/AT40KLV Series FPGA0896C–FPGA–04/02Figure 12. West I/O (Mirrored for East I/O) AT40K/AT40KLV(a) Primary I/O(b) Secondary I/OPADCELLCELLCELLTTL

21AT40K/AT40KLV Series FPGA0896C–FPGA–04/02Figure 13. South I/O (Mirrored for North I/O) AT40K/AT40KLVVCCTTL/CMOSGNDPULL-UPPADDRIVETRI-STATEPULL-DOWND

22AT40K/AT40KLV Series FPGA0896C–FPGA–04/02Figure 14. Northwest Corner (Similar for NE/SE/SW Corners) AT40K/AT40KLVCELLGNDPULL-UPPULL-DOWNTTL/CMOSDRIV

23AT40K/AT40KLV Series FPGA0896C–FPGA–04/02Absolute Maximum Ratings – 5V Commercial/Industrial* AT40KOperating Temperature...

24AT40K/AT40KLV Series FPGA0896C–FPGA–04/02DC Characteristics – 5V Operation Commercial/Industrial/Military AT40KSymbol Parameter Conditions Minimum T

25AT40K/AT40KLV Series FPGA0896C–FPGA–04/02AC Timing Characteristics – 5V Operation AT40KDelays are based on fixed loads and are described in the note

26AT40K/AT40KLV Series FPGA0896C–FPGA–04/02All input IO characteristics measured from a VIHof 50% at the pad (CMOS threshold) to the internal VIHof 50

27AT40K/AT40KLV Series FPGA0896C–FPGA–04/02AC Timing Characteristics – 5V Operation AT40KDelays are based on fixed loads and are described in the note

28AT40K/AT40KLV Series FPGA0896C–FPGA–04/02AC Timing Characteristics – 5V Operation AT40KDelays are based on fixed loads and are described in the note

29AT40K/AT40KLV Series FPGA0896C–FPGA–04/02FreeRAM Asynchronous Timing CharacteristicsSingle-port Write/ReadDual-port Write withReadDual-port Read01WE

3AT40K/AT40KLV Series FPGA0896C–FPGA–04/02Cache Logic Design The AT40K/AT40KLV, AT6000 and FPSLIC families are capable of implementingCache Logic (dyn

30AT40K/AT40KLV Series FPGA0896C–FPGA–04/02FreeRAM Synchronous Timing CharacteristicsSingle-port Write/ReadDual-port Write withReadDual-port ReadWEADD

31AT40K/AT40KLV Series FPGA0896C–FPGA–04/02Absolute Maximum Ratings – 3.3V Commercial/Industrial* AT40KLVOperating Temperature...

32AT40K/AT40KLV Series FPGA0896C–FPGA–04/02Note: 1. Parameter based on characterization and simulation; it is not tested in production.DC Characterist

33AT40K/AT40KLV Series FPGA0896C–FPGA–04/02AC Timing Characteristics – 3.3V Operation AT40KLVDelays are based on fixed loads and are described in the

34AT40K/AT40KLV Series FPGA0896C–FPGA–04/02AC Timing Characteristics – 3.3V Operation AT40KLVDelays are based on fixed loads and are described in the

35AT40K/AT40KLV Series FPGA0896C–FPGA–04/02AC Timing Characteristics – 3.3V Operation AT40KLVDelays are based on fixed loads and are described in the

36AT40K/AT40KLV Series FPGA0896C–FPGA–04/02Notes: 1. CMOS buffer delays are measured from a VIHof 1/2 VCCat the pad to the internal VIHat A. The input

37AT40K/AT40KLV Series FPGA0896C–FPGA–04/02AT40K05AT40K05LVAT40K10AT40K10LVAT4 0 K2 0AT40K20LVAT40K40AT40K40LV Left Side (Top to Bottom)128 I/O 192 I/

38AT40K/AT40KLV Series FPGA0896C–FPGA–04/02I/O11(A20)I/O15(A20)I/O19(A20)I/O27(A20)17 9 6 11 13 17 17 284 H25I/O12(A21)I/O16(A21)I/O20(A21)I/O28(A21)1

39AT40K/AT40KLV Series FPGA0896C–FPGA–04/02I/O20 I/O28 I/O36 I/O54 22 24 30 34 263 P24GNDI/O29 I/O37 I/O55 31 35 262 R26I/O30 I/O38 I/O56 32 36 261 R2

4AT40K/AT40KLV Series FPGA0896C–FPGA–04/02The SymmetricalArrayAt the heart of the Atmel architecture is a symmetrical array of identical cells,see Fig

40AT40K/AT40KLV Series FPGA0896C–FPGA–04/02I/O25 I/O41 I/O55 I/O83 30 40 50 241 Y24I/O26 I/O42 I/O56 I/O84 31 41 51 240 AA25GND GND GND(1)VCC VCC VCC(

41AT40K/AT40KLV Series FPGA0896C–FPGA–04/02I/O38(LDC)I/O54(LDC)I/O70(LDC)I/O102(LDC)37 33 30 44 48 62 68 221 AE23GNDI/O103I/O104I/O105 AC21I/O106 AD21

42AT40K/AT40KLV Series FPGA0896C–FPGA–04/02I/O87 I/O131 201 AE17I/O88 I/O132 200 AE16GND GND 83 GND(1)VCC VCC(1)I/O89 I/O133 199 AF16I/O90 I/O134 198

43AT40K/AT40KLV Series FPGA0896C–FPGA–04/02I/O106 I/O158 180 AD11I/O159 AE10I/O160 AC11I/O161I/O162GNDI/O79 I/O107 I/O163 99 179 AF9I/O80 I/O108 I/O16

44AT40K/AT40KLV Series FPGA0896C–FPGA–04/02GNDI/O187I/O188I/O61 I/O93 I/O125 I/O189 67 75 97 115 158 AD5I/O62 I/O94 I/O126 I/O190 68 76 98 116 157 AE3

45AT40K/AT40KLV Series FPGA0896C–FPGA–04/02I/O70 I/O104 I/O138 I/O206 59 56 80 88 114 130 141 AA2I/O71 I/O105 I/O139 I/O207 89 115 131 140 AA1I/O72 I/

46AT40K/AT40KLV Series FPGA0896C–FPGA–04/02GNDI/O77 I/O117 I/O157 I/O235 62 59 86 96 126 146 119 R1I/O78 I/O118 I/O158 I/O236 63 60 87 97 127 147 118

47AT40K/AT40KLV Series FPGA0896C–FPGA–04/02I/O88,FCK4I/O130,FCK4I/O174,FCK4I/O262,FCK499 109 141 163 98 J3I/O131 I/O175 I/O263 164 97 K4I/O132 I/O176

48AT40K/AT40KLV Series FPGA0896C–FPGA–04/02CCLK CCLK CCLK CCLK 73 77 74 107 119 153 179 78 C3VCC VCC VCC VCC 74 78 75 108 120 154 180 77 VCC(1)TSTCLK

49AT40K/AT40KLV Series FPGA0896C–FPGA–04/02I/O307I/O308I/O155 I/O205 I/O309 169 193 62 B7I/O156 I/O206 I/O310 170 194 61 A7I/O207 I/O311 195 60 D9I/O2

5AT40K/AT40KLV Series FPGA0896C–FPGA–04/02Figure 2. Floor Plan (Representative Portion)(1)Note: 1. Repeaters regenerate signals and can connect any bu

50AT40K/AT40KLV Series FPGA0896C–FPGA–04/02I/O112(A7)I/O168(A7)I/O224(A7)I/O336(A7)84 90 87 126 140 181 210 40 B14GND GND GND GND 1 91 88 127 141 182

51AT40K/AT40KLV Series FPGA0896C–FPGA–04/02I/O242 I/O362 17 D18I/O181 I/O243 I/O363 195 228 16 A21I/O182 I/O244 I/O364 196 229 15 B20I/O365I/O366GNDI/

52AT40K/AT40KLV Series FPGA0896C–FPGA–04/02Note: 1. In SBGA packages, Power and Ground pins do not connect directly to die. They connect to Power and

53AT40K/AT40KLV Series FPGA0896C–FPGA–04/02Part/Package Availability and User I/O Counts (including Dual-function Pins)Note: 1. Devices in same packag

54AT40K/AT40KLV Series FPGA0896C–FPGA–04/02Note: 1. For military parts, contact Atmel at [email protected]/AT40K05LV Ordering InformationUsable G

55AT40K/AT40KLV Series FPGA0896C–FPGA–04/02Note: 1. For military parts, contact Atmel at [email protected]/AT40K10LV Ordering InformationUsable G

56AT40K/AT40KLV Series FPGA0896C–FPGA–04/02Note: 1. For military parts, contact Atmel at [email protected]/AT40K20LV Ordering InformationUsable Ga

57AT40K/AT40KLV Series FPGA0896C–FPGA–04/02Note: 1. For military parts, contact Atmel at [email protected]/AT40K40LV Ordering InformationUsable G

58AT40K/AT40KLV Series FPGA0896C–FPGA–04/02Packaging Information84J – PLCC1.14(0.045) X 45˚PIN NO. 1IDENTIFIER1.14(0.045) X 45˚0.51(0.020)MAX0.318(0.0

59AT40K/AT40KLV Series FPGA0896C–FPGA–04/02100T1 – TQFP2325 Orchard ParkwaySan Jose, CA 95131TITLEDRAWING NO.RREV. 100T1 A11/30/01A1A2Bottom ViewSid

6AT40K/AT40KLV Series FPGA0896C–FPGA–04/02The Busing Network Figure 3 on page 7 depicts one of five identical busing planes. Each plane has three busr

60AT40K/AT40KLV Series FPGA0896C–FPGA–04/02100Q4 – PQFP2325 Orchard ParkwaySan Jose, CA 95131TITLEDRAWING NO.RREV. 100Q4 A3/29/02100Q4

61AT40K/AT40KLV Series FPGA0896C–FPGA–04/02144L1 – LQFP2325 Orchard ParkwaySan Jose, CA 95131TITLEDRAWING NO.RREV. 144L1 A11/30/01A1A2Bottom ViewSid

62AT40K/AT40KLV Series FPGA0896C–FPGA–04/02160Q1 – PQFP2325 Orchard ParkwaySan Jose, CA 95131TITLEDRAWING NO.RREV. 160Q1 A3/28/02160Q1

63AT40K/AT40KLV Series FPGA0896C–FPGA–04/02208Q1 – TQFP2325 Orchard ParkwaySan Jose, CA 95131 TITLEDRAWING NO.RREV. 208Q1 A11/30/01L1A2

64AT40K/AT40KLV Series FPGA0896C–FPGA–04/02240Q1 – PQFP2325 Orchard ParkwaySan Jose, CA 95131TITLEDRAWING NO.RREV. 240Q1 A3/29/02240Q1

65AT40K/AT40KLV Series FPGA0896C–FPGA–04/02304Q1 – PQFP2325 Orchard ParkwaySan Jose, CA 95131TITLEDRAWING NO.RREV. 304Q1 A3/29/02COMMO

66AT40K/AT40KLV Series FPGA0896C–FPGA–04/02352C1 – SBGA2325 Orchard ParkwaySan Jose, CA 95131TITLEDRAWING NO.RREV. 3/29/02352C1, 352-ball, 35 x 35,

Printed on recycled paper.© Atmel Corporation 2002.Atmel Corporation makes no warranty for the use of its products, other than those expressly contain

7AT40K/AT40KLV Series FPGA0896C–FPGA–04/02Figure 3. Busing Plane (One of Five)= Local/Local or Express/Express Turn Point= AT40K/AT40KLV Core Cell=

8AT40K/AT40KLV Series FPGA0896C–FPGA–04/02Cell Connections Figure 4(a) depicts direct connections between a cell and its eight nearest neighbors.Figur

9AT40K/AT40KLV Series FPGA0896C–FPGA–04/02Figure 5. The CellOUT OUTRESET/SETCLOCKFBX = Diagonal Direct Connect or BusY = Orthogonal Direct C