Rainbow-electronics ATF1504ASL Manual de usuario

1Features• High-density, High-performance, Electrically-erasable Complex ProgrammableLogic Device– 64 Macrocells– 5 Product Terms per Macrocell, Expan

10ATF1504AS(L)0950N–PLD–07/02Programming ATF1504AS devices are in-system programmable (ISP) devices utilizing the 4-pin JTAGprotocol. This capability

11ATF1504AS(L)0950N–PLD–07/02Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.2

12ATF1504AS(L)0950N–PLD–07/02Absolute Maximum Ratings*Temperature Under Bias... -40°Cto+85°C*NOTICE: Stresses beyond th

13ATF1504AS(L)0950N–PLD–07/02Note: See ordering information for valid part numbers.Timing ModelAC Characteristics (Continued)Symbol Parameter-7 -10 -1

14ATF1504AS(L)0950N–PLD–07/02Notes: 1. See ordering information for valid part numbers.2. The tRPAparameter must be added to the tLAD,tLAC,tTIC,tACL,a

15ATF1504AS(L)0950N–PLD–07/02Output AC Test LoadsNote: *Numbers in parenthesis refer to 3.0V operating conditions (preliminary).Power-down Mode The AT

16ATF1504AS(L)0950N–PLD–07/02JTAG-BST/ISPOverviewThe JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controllerin the ATF1504AS

17ATF1504AS(L)0950N–PLD–07/02BSC Configuration for Macrocell01DQ0101DQDQCaptureDRCaptureDRUpdateDR0101DQDQTDITDIOUTJOEJShiftShiftClockClockModeTDOTDOP

18ATF1504AS(L)0950N–PLD–07/02PCI Compliance The ATF1504AS also supports the growing need in the industry to support the newPeripheral Component Interc

19ATF1504AS(L)0950N–PLD–07/02Note: Leakage current is with pin-keeper off.Notes: 1. Equation A: IOH=11.9(VOUT- 5.25) * (VOUT+ 2.45) for VCC>VOUT>

2ATF1504AS(L)0950N–PLD–07/0244-lead TQFPTop View12345678910113332313029282726252423I/O/TDII/OI/OGNDPD1/I/OI/OTMS/I/OI/OVCCI/OI/OI/OI/O/TDOI/OI/OVCCI/O

20ATF1504AS(L)0950N–PLD–07/02OE (1, 2) Global OE PinsGCLR Global Clear PinGCLK (1, 2, 3) Global Clock PinsPD (1, 2) Power down pinsTDI, TMS, TCK, TDO

21ATF1504AS(L)0950N–PLD–07/02ATF1504AS I/O PinoutsMC PLC44-leadPLCC44-leadTQFP68-leadPLCC84-leadPLCC100-leadPQFP100-leadTQFP MC PLC44-leadPLCC44-leadT

22ATF1504AS(L)0950N–PLD–07/02SUPPLY CURRENT VS. SUPPLY VOLTAGE(TA=25°C, F = 0)02550751001254.50 4.75 5.00 5.25 5.50VCC(V)ICC(mA)STANDARDREDUCED POWER

23ATF1504AS(L)0950N–PLD–07/02OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE(VOL = 0.5V, TA=25°C)343536373839404142434.50 4.75 5.00 5.25 5.50SUPPLY VOLTAGE (V)

24ATF1504AS(L)0950N–PLD–07/02NORMALIZED TCOVS.TEMPERATURE (VCC=5.0V)0.80.91.01.11.2-40.0 0.0 25.0 75.0TEMPERATURE (C)NORMALIZED TCONORMALIZED TSUVS. T

25ATF1504AS(L)0950N–PLD–07/02Using “C” Product for IndustrialTo use commercial product for Industrial temperature ranges, down-grade one speed grade f

26ATF1504AS(L)0950N–PLD–07/02Using “C” Product for IndustrialTo use commercial product for Industrial temperature ranges, down-grade one speed grade f

27ATF1504AS(L)0950N–PLD–07/02Packaging Information44A – TQFP 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 44A, 44-lead, 10 x 10 mm

28ATF1504AS(L)0950N–PLD–07/0244J – PLCCNotes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include

29ATF1504AS(L)0950N–PLD–07/0268J – PLCC 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 68J, 68-lead, Plastic J-leaded Chip Carrier (

3ATF1504AS(L)0950N–PLD–07/02100-lead PQFPTop View12345678910111213141516171819202122232425262728293080797877767574737271706968676665646362616059585756

30ATF1504AS(L)0950N–PLD–07/0284J – PLCC 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 84J, 84-lead, Plastic J-leaded Chip Carrier (

31ATF1504AS(L)0950N–PLD–07/02100Q1 – PQFPPIN 1 ID16.95 (0.667)17.45 (0.687)19.90 (0.783)20.10 (0.791)22.95 (0.904)23.45 (0.923)0.65 (0.0256) BSC0.22 (

32ATF1504AS(L)0950N–PLD–07/02100A – TQFP 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 100A, 100-lead, 14 x 14 mm Body Size, 1.0 mm

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4ATF1504AS(L)0950N–PLD–07/02Description The ATF1504AS is a high-performance, high-density complex programmable logicdevice (CPLD) that utilizes Atmel’

5ATF1504AS(L)0950N–PLD–07/02Block DiagramUnused product terms are automatically disabled by the compiler to decrease powerconsumption. A security fuse

6ATF1504AS(L)0950N–PLD–07/02Product Terms and SelectMuxEach ATF1504AS macrocell has five product terms. Each product term receives as itspossible inpu

7ATF1504AS(L)0950N–PLD–07/02Foldback Bus Each macrocell also generates a foldback product term. This signal goes to the regionalbus and is available t

8ATF1504AS(L)0950N–PLD–07/02Programmable Pin-keeper Option forInputs and I/OsThe ATF1504AS offers the option of programming all input and I/O pins so

9ATF1504AS(L)0950N–PLD–07/02All pin transitions are ignored until the PD pin is brought low. When the power-down fea-ture is enabled, the PD1 or PD2 p