
10
AT77C105A [Preliminary]
5419A–BIOM–01/05
Timing Diagrams: Slow and Fast SPI Interface
Figure 3. Read Timing Fast SPI Slave Mode
Figure 4. Read/Write Timing Slow SPI Slave Mode
Figure 5. Read Status Register to Release IRQ
Figure 6. Chip Initialization
T
sshd
T
dis
T
v
RST
SS
SCK
MISO
T
rstsu
T
sssu
DC
SS
SCK
MOSI
MISO
T
sssu
T
su
T
h
T
sshd
SS
SCK
MOSI
IRQ
T
irq
11 0 0 0 X
0X
RST
SS
SCK
MISO
Min = 10 µs
T
rstsu
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