
Power-Management ICs for
ICERA E400/E450 Platform
MAX8982A/MAX8982X
52
Table 26. LED3FT5 Register (LED3 (DR3) Flash Timer t
4
Setting)
Table 27. LED3FT6 Register (LED3 (DR3) Flash Timer t
P
Setting)
Table 28. BUCK1 Register (On/Off Control for BUCK1)
ADDRESS
(HEX)
POR
(HEX)
R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
2C 00 R/W Reserved LD3T4[6:0]
NAME POR DESCRIPTION
LD3T4[6:0] 0000000
BIT
t
4
TIME
(ms)
6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 1 25
0 0 0 0 0 1 0 50
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1 1 1 1 1 1 1 3175
From 0ms to 3175ms in 25ms increments.
ADDRESS
(HEX)
POR
(HEX)
R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
2D 00 R/W Reserved LD3TP[6:0]
NAME POR DESCRIPTION
LD3TP[6:0] 0000000
BIT
t
P
TIME
(ms)
6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 1 25
0 0 0 0 0 1 0 50
0 0 0 0 0 1 1 75
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1 1 1 1 1 1 1 3175
From 0ms to 3175ms in 25ms increments.
ADDRESS
(HEX)
POR
(HEX)
R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
3D 47 R/W Reserved Reserved Reserved Reserved Reserved Reserved BUCK1[1:0]
BITS 7:2 Reserved, write 010001 to these bits.
BIT 1 BIT 0 DESCRIPTION
0 0 BUCK1 off (in I
2
C on mode).
0 1 BUCK1 on (in I
2
C on mode).
1 0 BUCK1 on (in PWR_REQ on mode) (Group D).
1 1 BUCK1 on (in PWR_REQ on mode) (Group D).
Comentarios a estos manuales