
MAX1519/MAX1545
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, V
CC
= V
DD
= V
SHDN
= V
TON
= V
SKIP
= V
S0
= V
S1
= V
CODE
= 5V, V
FB
= V
CMP
= V
CMN
= V
CSP
= V
CSN
= 1.3V, OFS = SUS = GNDS = D0–D4 = GND; T
A
= 0°C to +85°C, unless otherwise specified. Typical values are at T
A
= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
GATE DRIVERS
DH_ Gate-Driver On-Resistance R
ON(DH)
BST_ - LX_ forced to 5V 1.0 4.5 Ω
High state (pullup) 1.0 4.5
DL_ Gate-Driver On-Resistance R
ON(DL)
Low start (pulldown) 0.4 2
Ω
DH_ Gate-Driver Source/Sink
Current
I
DH
DH_ forced to 2.5V,
BST_ - LX_ forced to 5V
1.6 A
DL_ Gate-Driver Sink Current I
DL
SINK
DL_ forced to 5V 4 A
DL_ Gate-Driver Source Current I
DL
SOURCE
DL_ forced to 2.5V 1.6 A
DL_ rising 35
Dead Time t
DEAD
DH_ rising 26
ns
VOLTAGE-POSITIONING AMPLIFIER
Input Offset Voltage V
OS
-1 +1 mV
Input Bias Current I
BIAS
OAIN+, OAIN- 0.1 200 nA
Op Amp Disable Threshold V
OAIN-
3V
CC
- 1
V
CC
-
0.4
V
Common-Mode Input Voltage
Range
V
CM
Guaranteed by CMRR test 0 2.5 V
Common-Mode Rejection Ratio CMRR V
OAIN+
= V
OAIN-
= 0 to 2.5V 70 115 dB
Power-Supply Rejection Ratio PSRR V
CC
= 4.5V to 5.5V 75 100 dB
Large-Signal Voltage Gain A
OA
R
L
= 1kΩ to V
CC
/2 80 112 dB
V
CC
- V
FBH
77 300
Output Voltage Swing
|V
OAIN+
- V
OAIN-
| ≥ 10mV,
R
L
= 1kΩ to V
CC
/2
V
FBL
47 200
mV
Input Capacitance 11 pF
Gain-Bandwidth Product 3 MHz
Slew Rate 0.3 V/µs
Capacitive-Load Stability No sustained oscillations 400 pF
LOGIC AND I/O
SHDN Input High Voltage V
IH
0.8 V
SHDN Input Low Voltage V
IL
0.4 V
SHDN No-Fault Threshold V
SHDN
12 15 V
High 2.7
REF 1.2 2.3
Three-Level Input Logic Levels SUS, SKIP
Low 0.8
V
Logic Input Current SHDN, SUS, SKIP -1 +1 µA
D0–D4 Logic Input High Voltage 1.6 V
D0–D4 Logic Input Low Voltage 0.8 V
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