Rainbow-electronics ATmega8HVD Manual de usuario descargar pdf (Pagina 54)

8052B–AVR–09/08

ATmega4HVD/8HVD

be changed. Finally, the INTn interrupt flags should be cleared by writing a logical one to its

Interrupt Flag bit (INTFn) in the EIFR Register before the interrupt is re-enabled.

Note: 1. n = 1 or 0.

When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt

Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are

changed.

12.1.2 EIMSK – External Interrupt Mask Register

• Bits 7:2 – RES: Reserved Bits

These bits are reserved bits in the ATmega4HVD/8HVD, and will always read as zero.

• Bit 1:0 – INT1:0: External Interrupt Request 1:0 Enable

When the INT1 - INT0 bit is written to one and the I-bit in the Status Register (SREG) is set

(one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in

the External Interrupt Control Register – EICRA – defines whether the external interrupt is acti-

vated on rising or falling edge or level sensed. Activity on this pin will trigger an interrupt

request even if the pin is enabled as an output. This provides a way of generating a software

interrupt.

12.1.3 EIFR – External Interrupt Register

• Bits 7:2 – RES: Reserved Bits

These bits are reserved bits ins the ATmega4HVD/8HVD, and will always read as zero.

• Bits 1:0 – INTF1:0: External Interrupt Flag 1:0

When an edge or logic change on the INT1:0 pin triggers an interrupt request, INTF1:0

becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT1:0 in

EIMSK, are set (one), the MCU will jump to the interrupt vector. The flag is cleared when the

Table 12-1. Interrupt Sense Control

ISCn1 ISCn0 Description

0 0 The low level of INTn generates an interrupt request.

0 1 Any logical change on INTn generates an interrupt request.

1 0 The falling edge of INTn generates an interrupt request.

1 1 The rising edge of INTn generates an interrupt request.

Bit 76543210

––––––INT1INT0EIMSK

Read/WriteRRRRRRR/WR/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

– – – – – – INTF1 INTF0 EIFR

Read/WriteRRRRRRRR

Initial Value 0 0 0 0 0 0 0 0

1 2 ... 49 50 51 52 53 54 55 56 57 58 59 ... 167 168

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Rainbow-electronics ATmega8HVD Manual de usuario Pagina 54