Rainbow-electronics ATmega64L Manual de usuario descargar pdf (Pagina 212)

212

ATmega16(L)

2466B–09/01

The ADC Data Register –

ADCL and ADCH

ADLAR = 0:

ADLAR = 1:

When an ADC conversion is complete, the result is found in these two registers. If differ-

ential channels are used, the result is presented in two’s complement form.

When ADCL is read, the ADC Data Register is not updated until ADCH is read. Conse-

quently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for

differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL

must be read first, then ADCH.

The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is

read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared

(default), the result is right adjusted.

• ADC9:0: ADC Conversion Result

These bits represent the result from the conversion, as detailed in “ADC Conversion

Result” on page 208.

Table 84. ADC Prescaler Selections

ADPS2 ADPS1 ADPS0 Division Factor

000 2

001 2

010 4

011 8

100 16

101 32

110 64

111 128

Bit 151413121110 9 8

––––––ADC9 ADC8 ADCH

ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL

76543210

Read/WriteRRRRRRRR

RRRRRRRR

Initial Value00000000

00000000

Bit 151413121110 9 8

ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH

ADC1 ADC0 ––––––ADCL

76543210

Read/WriteRRRRRRRR

RRRRRRRR

Initial Value00000000

00000000

1 2 ... 207 208 209 210 211 212 213 214 215 216 217 ... 297 298

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