Rainbow-electronics ATmega64L Manual de usuario descargar pdf (Pagina 15)

15

ATmega16(L)

2466B–09/01

Data Memory Access Times This section describes the general access timing concepts for internal memory access.

The internal data SRAM access is performed in two clk

CPU

cycles as described in Figure

10.

Figure 10. On-chip Data SRAM Access Cycles

clk

WR

RD

Data

Data

Address

Address Valid

T1 T2 T3

Compute Address

Read

Write

CPU

Memory Access Instruction

Next Instruction

1 2 ... 10 11 12 13 14 15 16 17 18 19 20 ... 297 298

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