
MAX3798
1.0625Gbps to 10.32Gbps, Integrated, Low-
Power SFP+ Limiting Amplifier and VCSEL Driver
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REGISTER
FUNCTION/
ADDRESS
REGISTER
NAME
NORMAL
MODE
SETUP
MODE
BIT
NUMBER
/TYPE
BIT NAME
DEFAULT
VALUE
NOTES
R RW 3 CAZX 1
External autozero capacitor
0: disconnected, 1:
connected
R RW 2 GMEN 1
Mode-select switching time
boost
0: off, 1: on
R RW 1 MODE_SEL 0
Mode-select
0: high-gain mode, 1: high-
bandwidth mode
Receiver Control
Register 1
Address = H0x00
RXCTRL1
R RW 0 SLEW_RATE 0
Slew-rate select
0: slow mode, 1: fast mode
R RW 6 LOS_EN 1
LOS control
0: disable, 1: enable
(always 0 when RX_EN = 0)
R RW 5 LOS_POL 1
LOS polarity
0: inverse, 1: normal
R RW 4 RX_POL 1
Rx polarity
0: inverse, 1: normal
R RW 3 SQ_EN 0
Squelch
0: disable, 1: enable
R RW 2 RX_EN 1
Rx control
0: disable, 1: enable
R RW 1 RXDE_EN 0
Rx deemphasis
0: disable, 1: enable
Receiver Control
Register 2
Address = H0x01
RXCTRL2
R RW 0 AZ_EN 1
Rx autozero control
0: disable, 1: enable
(always 0 when RX_EN = 0)
Receiver Status
Register
Address = H0x02
RXSTAT R R 0 (sticky) LOS X Copy of LOS output signal
R RW 7 SET_CML[7] 0 MSB output level DAC
R RW 6 SET_CML[6] 1
R RW 5 SET_CML[5] 0
R RW 4 SET_CML[4] 1
R RW 3 SET_CML[3] 0
R RW 2 SET_CML[2] 0
R RW 1 SET_CML[1] 1
Output CML Level
Setting Register
Address = H0x03
SET_CML
R RW 0 SET_CML[0] 1 LSB output level DAC
Table 7. Register Summary
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