MAX3798
1.0625Gbps to 10.32Gbps, Integrated, Low-
Power SFP+ Limiting Amplifier and VCSEL Driver
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Bit 2: RX_EN. Enables or disables the receive circuitry.
0 = disabled
1 = enabled
Bit 1: RXDE_EN. Enables or disables the deemphasis on the receiver output.
0 = disabled
1 = enabled
Bit 0: AZ_EN. Enables or disables the autozero circuitry. When RX_EN is set to 0, the autozero circuitry is also disabled.
0 = disabled
1 = enabled
Receiver Status Register (RXSTAT)
Bit 0: LOS. Copy of the LOS output circuitry. This is a sticky bit, which means that it is cleared on a read. The first 0-
to-1 transition gets latched until the bit is read by the master or POR occurs.
Output CML Level Setting Register (SET_CML)
Bits 7 to 0: SET_CML[7:0]. The SET_CML register is an 8-bit register that can be set to range from 0 to 255, corre-
sponding from 40mV
P-P
to 1200mV
P-P
. See the
Typical Operating Characteristics
section for a typical CML output
voltage vs. DAC code graph.
LOS Threshold Level Setting Register (SET_LOS)
Bits 5 to 0: SET_LOS[5:0]. The SET_LOS register is a 6-bit register used to program the LOS threshold. See the
Typical Operating Characteristics
section for a typical LOS threshold voltage vs. DAC code graph.
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