
PRELIMINARY DS2432
14 of 30
Memory and SHA Functions Flow Chart (continued) Figure 7
F0h
Read Memory ?
Address
< 98h ?
N
Bus Master TX
TA1 (T7:T0),
TA2 (T15:T8)
N
N
Address
Of Secret
DS2432 sets Memory
Address = (T15:T0)
DS2432
Increments
Address
Counter
Bus Master
RX “1”s
N
Address
< 97h ?
Master
TX Reset ?
N
Master
TX Reset ?
Bus Master RX
Data Byte from
Memory Address
Bus Master
RX FFh Byte
N
From Figure 7
6
th
Part
To Figure 7
6
th
Part
N
Bus Master
RX “1”s
Master
TX Reset ?
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