Rainbow-electronics MAX1386 Manual de usuario descargar pdf (Pagina 42)

MAX1385/MAX1386

Dual RF LDMOS Bias Controllers

with I

C/SPI Interface

42 ______________________________________________________________________________________

Acknowledge Bits

Data transfers are acknowledged with an acknowledge

bit (ACK) or a not-acknowledge bit (NACK). Both the

master and the MAX1385/MAX1386 generate ACK bits.

To generate an ACK, SDA must be pulled low before

the rising edge of the ninth clock pulse and kept low

during the high period of the ninth clock pulse (see

Figure 20). To generate a NACK, SDA is pulled high

before the rising edge of the ninth clock pulse and is

left high for the duration of the ninth clock pulse.

Monitoring NACK bits allow for detection of unsuccess-

ful data transfers. NACK bits can also be used by the

master to interrupt the current data transfer to start

another data transfer. The MAX1385/MAX1386 do not

issue an ACK after the last byte of a full reset write to

the Software Clear register.

Fast/High-Speed Modes

At power-up, the bus timing is set for slow-/fast-speed

mode (FS mode), which allows bus speeds up to

400kHz. The MAX1385/MAX1386 are configurable for

S OR Sr

ADDRESS

ACK

WRITE

COMMAND

ACK DATA ACK

7 BITS

DATA

ACK

ADDRESS

DATA

ACK

DATA

Sr OR P

NACK

ACK

R/W

8 BITS (MSB)

8 BITS (LSB)

8 BITS

7 BITS

8 BITS (MSB) 8 BITS (LSB)

R/W

Figure 12. Write/Readback Sequence

S OR Sr

ADDRESS

ACK

READ

COMMAND

ACK

7 BITS

ADDRESS

DATA

ACK

DATA

Sr OR P

NACK

ACK

R/W

8 BITS

7 BITS

8 BITS (MSB)

8 BITS (LSB)

R/W

7 BITS

ADDRESS

ACK

R/W

WRITE

COMMAND

ACK

DATA

ACK

DATA

ACK

8 BITS

8 BITS (MSB)

8 BITS (LSB)

Figure 13. Read-Modify-Write Sequence

SDA

SCL

10 0A2A1A0

ACK

R/W

Figure 14. Slave Address Byte

1 2 ... 37 38 39 40 41 42 43 44 45 46 47 ... 51 52

MAX1385/MAX1386 1
C/SPI Interface 1

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