Rainbow-electronics ATF20V8CQZ Manual de usuario descargar pdf (Pagina 2)

ATF20V8C Family

0408H–04/01

Block Diagram

Description

The ATF20V8C is a high-performance CMOS (electrically

erasable) programmable logic device (PLD) that utilizes

Atmel’s proven electrically erasable technology. Speeds

down to 5 ns and power dissipation as low as 10 µA are

offered. All speed ranges are specified over the full 5V ±

10% range for industrial temperature ranges, and 5V ± 5%

for commercial ranges.

The ATF20V8C(Q) provides a high-speed CMOS PLD

solution with maximum pin-to-pin delay of 5 ns. The

ATF20V8C(Q) also has a user-controlled power-down fea-

ture, offering “zero” standby power (10 µA typical). The

user-controlled power-down feature allows the user to

manage total system power to meet specific application

requirements and enhance reliability without sacrificing

speed.

The ATF20V8CQZ provides the zero power CMOS PLD

solution, with “zero” standby power (10 µA typical). The

device powers down automatically through Atmel’s pat-

ented Input Transition Detection (ITD) circuitry to the “zero”

standby power mode when all inputs are idle.

Pin “keeper” circuits on input and output pins reduce static

power consumed by pull-ups.

The ATF20V8C(Q)(Z) is the industry-standard 20V8 archi-

tecture. Eight outputs are each allocated eight product

terms. Three different modes of operation, configured auto-

matically with software, allow highly complex logic

functions to be realized.

Power-up Reset

The registers in the ATF20V8Cs are designed to reset dur-

ing power-up. At a point delayed slightly from V

crossing

RST

, all registers will be reset to the low state. As a result,

the registered output state will always be high on power-up.

This feature is critical for state machine initialization. How-

ever, due to the asynchronous nature of reset and the

uncertainty of how V

actually rises in the system, the fol-

lowing conditions are required:

1. The V

rise must be monotonic,

2. After reset occurs, all input and feedback setup

times must be met before driving the clock pin high,

and

3. The clock must remain stable during t

Preload of Registered Outputs

The ATF20V8C registers are provided with circuitry to

allow loading of each register with either a high or a low.

This feature will simplify testing since any state can be

forced into the registers to control test sequencing. A

JEDEC file with preload is generated when a source file

with vectors is compiled. Once downloaded, the JEDEC file

preload sequence will be done automatically by most of the

approved programmers after the programming.

Electronic Signature Word

There are 64 bits of programmable memory that are always

available to the user, even if the device is secured. These

bits can be used for user-specific data.

1 2 3 4 5 6 7 ... 29 30

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