Rainbow-electronics T89C51CC01 Manual de usuario descargar pdf (Pagina 9)

T89C51CC01

Rev. D – 17-Dec-01

Figure 3. Port 2 Structure

Notes: 1. Port 2 is precluded from use as general purpose I/O Ports when as address/data bus

drivers.

2. Port 2 internal strong pull-ups FET (P1 in FiGURE) assist the logic-one output for

memory bus cycle.

When Port 0 and Port 2 are used for an external memory cycle, an internal control signal

switches the output-driver input from the latch output to the internal address/data line.

4.5 Read-Modify-Write

Instructions

Some instructions read the latch data rather than the pin data. The latch based instruc-

tions read the data, modify the data and then rewrite the latch. These are called "Read-

Modify-Write" instructions. Below is a complete list of these special instructions (see

Table 1). When the destination operand is a Port or a Port bit, these instructions read

the latch rather than the pin:

Table 1. Read-Modify-Write Instructions

P2.X

LATCH

INTERNAL

WRITE

LATCH

READ

LATCH

P2.x (1)

ADDRESS HIGH/

CONTROL

BUS

VDD

INTERNAL

PULL-UP (2)

Instruction Description Example

ANL logical AND ANL P1, A

ORL logical OR ORL P2, A

XRL logical EX-OR XRL P3, A

JBC jump if bit = 1 and clear bit JBC P1.1, LABEL

CPL complement bit CPL P3.0

INC increment INC P2

DEC decrement DEC P2

DJNZ decrement and jump if not zero DJNZ P3, LABEL

MOV Px.y, C move carry bit to bit y of Port x MOV P1.5, C

CLR Px.y clear bit y of Port x CLR P2.4

SET Px.y set bit y of Port x SET P3.3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 ... 148 149

T89C51CC01 1

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