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T89C51CC01
Rev. D – 17-Dec-01
Table 94. IPH1 Register
IPH1 (S:FFh)
Interrupt high priority Register 1
Reset Value = XXXX X000b
76543210
- - - - POVRH PADCH PCANH
Bit
Number
Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2POVRH
Timer overrun Interrupt Priority level most significant bit
POVRH
POVRLPriority level
00Lowest
01
10
11Highest
1 PADCH
ADC Interrupt Priority level most significant bit
PADCH
PADCL Priority level
00Lowest
01
10
11Highest
0 PCANH
CAN Interrupt Priority level most significant bit
PCANH
PCANLPriority level
00Lowest
01
10
11Highest
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