
59
T89C5115
4128A–8051–04/02
Registers Table 37. T2CON Register
T2CON (S:C8h)
Timer 2 Control Register
Reset Value = 0000 0000b
Bit addressable
76543210
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#
Bit
Number
Bit
Mnemonic Description
7TF2
Timer 2 overflow Flag
TF2 is not set if RCLK=1 or TCLK = 1.
Must be cleared by software.
Set by hardware on Timer 2 overflow.
6EXF2
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin if
EXEN2=1.
Set to cause the CPU to vector to Timer 2 interrupt routine when Timer 2
interrupt is enabled.
Must be cleared by software.
5RCLK
Receive Clock bit
Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3.
4TCLK
Transmit Clock bit
Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3.
3 EXEN2
Timer 2 External Enable bit
Clear to ignore events on T2EX pin for Timer 2 operation.
SettocauseacaptureorreloadwhenanegativetransitiononT2EXpinis
detected, if Timer 2 is not used to clock the serial port.
2TR2
Timer 2 Run control bit
Clear to turn off Timer 2.
SettoturnonTimer2.
1C/T2#
Timer/Counter 2 select bit
Clear for timer operation (input from internal clock system: F
OSC
).
Set for counter operation (input from T2 input pin).
0CP/RL2#
Timer 2 Capture/Reload bit
If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on
Timer 2 overflow.
Clear to auto-reload on Timer 2 overflows or negative transitions on T2EX pin if
EXEN2=1.
Set to capture on negative transitions on T2EX pin if EXEN2=1.
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