
25
T89C5115
4128A–8051–04/02
Table 17. AUXR1 Register
AUXR1 (S:A2h)
Auxiliary Control Register 1
Reset Value = xxxx 00x0b
76543210
– – ENBOOT – GF3 0 – DPS
Bit
Number
Bit
Mnemonic Description
7-6
–
Reserved
The value read from these bits is indeterminate. Do not set these bits.
5 ENBOOT
Enable Boot Flash
Set this bit for map the boot flash between F800h -FFFFh
Clear this bit for disable boot flash.
4
–
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3GF3General-purpose Flag 3.
20
Always Zero
This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3
flag.
1 – Reserved for Data Pointer Extension.
0DPS
Data Pointer Select Bit
Set to select second dual data pointer: DPTR1.
Clear to select first dual data pointer: DPTR0.
Comentarios a estos manuales