MAX5098A
Dual, 2.2MHz, Automotive Buck or Boost
Converter with 80V Load-Dump Protection
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDRV = V
L
, V+ = V
L
= IN_HIGH = 5.2V or V+ = IN_HIGH = 5.2V to 19V, EN_ = V
L
, SYNC = GND, I
VL
= 0mA, PGND_ = SGND,
C
BYPASS
= 0.22µF (low ESR), C
VL
= 4.7µF (ceramic), C
V+
= 1µF (low ESR), C
IN_HIGH
= 1µF (ceramic), R
IN_HIGH
= 3.9kΩ, R
OSC
= 10kΩ,
T
J
= -40°C to +125°C, unless otherwise noted.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
I
SWITCH
= 100mA, BST2/VDD2 to
V
SOURCE2
= 5.2V
280
On-Resistance High-Side
MOSFET Converter 2
R
ON2
I
SWITCH
= 100mA, BST2/VDD2 to
V
SOURCE2
= 4.5V
300 520
mΩ
Minimum Converter 1 Output
Current
I
OUT1
V
OUT1
= 5V, V+ = 12V (Note 4) 2 A
Minimum Converter 2 Output
Current
I
OUT2
V
OUT2
= 3.3V, V+ = 12V (Note 4) 1 A
Converter 1/Converter 2
MOSFET DRAIN_ Leakage
Current
I
LK12
V
EN1
= V
EN2
= 0V, V
DRAIN_
= 19V,
V
SOURCE_
= 0V
20 µA
Internal Weak Low-Side Switch
On-Resistance
R
ONLSSW_
I
LSSW
= 30mA 22 Ω
INTERNAL SWITCH CURRENT LIMIT
Internal Switch Current-Limit
Converter 1
I
CL1
V+ = V
IN_HIGH
= 5.2V, V
L
= VDRV =
V
BST_/VDD_
= 5.2V
2.8 3.45 4.3 A
Internal Switch Current-Limit
Converter 2
I
CL2
V+ = V
IN_HIGH
= 5.2V, V
L
= VDRV =
V
BST_/VDD_
= 5.2V
1.75 2.1 2.6 A
SWITCHING FREQUENCY
PWM Maximum Duty Cycle D
MAX
SYNC = SGND, f
SW
= 1.25MHz 82 90 95 %
Switching Frequency Range f
SW
200 2200 kHz
Switching Frequency f
SW
R
OSC
= 6.81kΩ, each converter
(FSEL_1 = V
L
)
1.7 1.9 2.1 MHz
5.6kΩ < R
OSC
< 10kΩ, 1% 5
Switching Frequency Accuracy
10kΩ < R
OSC
< 62.5kΩ, 1% 7
%
SYNC Frequency Range f
SYNC
SYNC input frequency is twice the
individual converter frequency,
FSEL_1 = V
L
(see the Setting the
Switching Frequency section)
400 4400 kHz
SYNC High Threshold V
SYNCH
2V
SYNC Low Threshold V
SYNCL
0.8 V
SYNC Input Leakage I
SYNC_LEAK
2µA
SYNC Input Minimum Pulse
Width
t
SYNCIN
100 ns
Clock Output Phase Delay CKO
PHASE
R
OSC
= 62.5kΩ, with respect to converter
2/SOURCE2 waveform
40 D eg r ees
SYNC to Source 1 Phase Delay SYNC
PHASE
R
OSC
= 62.5kΩ 90 D eg r ees
Clock Output High Level V
CKOH
V
L
= 5.2V, sourcing 5mA 3.6 V
Clock Output Low Level V
CKOL
V
L
= 5.2V, sinking 5mA 0.6 V
(6 paginas)
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