37
ATtiny26(L)
1477B–AVR–04/02
Timer/Counter Interrupt Flag
Register – TIFR
• Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny26/L and always reads as zero.
• Bit 6 – OCF1A: Output Compare Flag 1A
The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and
the data value in OCR1A – Output Compare Register 1A. OCF1A is cleared by hard-
ware when executing the corresponding interrupt handling vector. Alternatively, OCF1A
is cleared, after synchronization clock cycle, by writing a logic one to the flag. When the
I-bit in SREG, OCIE1A, and OCF1A are set (one), the Timer/Counter1 A Compare
Match interrupt is executed.
• Bit 5 – OCF1B: Output Compare Flag 1B
The OCF1B bit is set (one) when compare match occurs between Timer/Counter1 and
the data value in OCR1B – Output Compare Register 1A. OCF1B is cleared by hard-
ware when executing the corresponding interrupt handling vector. Alternatively, OCF1B
is cleared, after synchronization clock cycle, by writing a logic one to the flag. When the
I-bit in SREG, OCIE1B, and OCF1B are set (one), the Timer/Counter1 B Compare
Match interrupt is executed.
• Bits 4..3 – Res: Reserved Bits
These bits are reserved bits in the ATtiny26/L and always read as zero.
• Bit 2 – TOV1: Timer/Counter1 Overflow Flag
The bit TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV1 is cleared, after synchronization clock cycle, by writing a logical one to the flag.
When the SREG I-bit, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and
TOV1 are set (one), the Timer/Counter1 Overflow interrupt is executed.
• Bit 1 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV0 is cleared by writing a logical one to the flag. When the SREG I-bit, and TOIE0
(Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the
Timer/Counter0 Overflow interrupt is executed.
• Bit 0 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny26/L and always reads as zero.
Bit 7 6 5 4 3 2 1 0
$38 ($58) – OCF1A OCF1B ––TOV1 TOV0 – TIFR
Read/Write R R/W R/W R R R/W R/W R
Initial Value 0 0 0 0 0 0 0 0
(18 paginas)
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