Rainbow-electronics ATmega64M1 Manual de usuario descargar pdf (Pagina 162)

162

8209A–AVR–08/09

ATmega16M1/32M1/64M1

19.5.3 SPSR – SPI Status Register

• Bit 7 – SPIF: SPI Interrupt Flag

When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in

SPCR is set and global interrupts are enabled. If SS

is an input and is driven low when the SPI is

in Master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the

corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the

SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).

• Bit 6 – WCOL: Write COLlision Flag

The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The

WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set,

and then accessing the SPI Data Register.

• Bit 5:1 – Res: Reserved

These bits are reserved and will always read as zero.

• Bit 0 – SPI2X: Double SPI Speed Bit

When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI

is in Master mode (see Table 19-5). This means that the minimum SCK period will be two CPU

clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at f

clkio

or lower.

The SPI interface on the ATmega16M1/32M1/64M1 is also used for program memory and

EEPROM downloading or uploading. See “Serial Programming Algorithm” on page 306 for serial

programming and verification.

Table 19-5. Relationship Between SCK and the Oscillator Frequency

SPI2X SPR1 SPR0 SCK Frequency

000

clkio

001

clkio

/16

010f

clkio

/64

011f

clkio

/128

100f

clkio

101

clkio

110f

clkio

/32

111f

clkio

/64

Bit 76543210

SPIFWCOL–––––SPI2XSPSR

Read/Write RRRRRRRR/W

Initial Value 00000000

1 2 ... 157 158 159 160 161 162 163 164 165 166 167 ... 342 343

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