Rainbow-electronics ATmega64M1 Manual de usuario descargar pdf (Pagina 219)

219

8209A–AVR–08/09

ATmega16M1/32M1/64M1

• Bit 3 - LENA: Enable

– 0 = Disable (both LIN and UART modes),

– 1 = Enable (both LIN and UART modes).

• Bit 2:0 - LCMD[2:0]: Command and mode

The command is only available if LENA is set, and is set according to Table 21-7.

21.6.2 LINSIR – LIN Status and Interrupt Register

• Bits 7:5 - LIDST[2:0]: Identifier Status

The LIN Identifier status is set according to Table 21-8.

• Bit 4 - LBUSY: Busy Signal

– 0 = Not busy,

– 1 = Busy (receiving or transmitting).

• Bit 3 - LERR: Error Interrupt

It is a logical OR of LINERR register bits. This bit generates an interrupt if its respective

enable bit - LENERR - is set in LINENIR.

–0 = No error,

– 1 = An error has occurred.

Table 21-7. LIN Commanads

LCMD[2:0] Mode

000

LIN Rx Header - LIN abort

001

LIN Tx Header

010

LIN Rx Response

011

LIN Tx Response

100 UART Rx & Tx Byte disable

11x UART Rx Byte enable

1x1 UART Tx Byte enable

Bit 76543210

LIDST2 LIDST1 LIDST0 LBUSY LERR LIDOK LTXOK LRXOK

LINSIR

Read/WriteRRRRR/W

one

R/W

one

R/W

one

R/W

one

Initial Value00000000

Table 21-8. LIN Identifier Status

LIDST[2:0] Status

0xx

No specific identifier

100

Identifier 60 (0x3C)

101

Identifier 61 (0x3D)

110

Identifier 62 (0x3E)

111

Identifier 63 (0x3F)

1 2 ... 214 215 216 217 218 219 220 221 222 223 224 ... 342 343

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