Rainbow-electronics ATmega64C1 Manual de usuario Pagina 260

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7647A–AVR–02/08
ATmega32/64/M1/C1
20.4 Analog Comparator Register Description
Each analog comparator has its own control register.
A dedicated register has been designed to consign the outputs and the flags of the 4 analog
comparators.
20.4.1 Analog Comparator 0 Control Register – AC0CON
Bit 7– AC0EN: Analog Comparator 0 Enable Bit
Set this bit to enable the analog comparator 0.
Clear this bit to disable the analog comparator 0.
Bit 6– AC0IE: Analog Comparator 0 Interrupt Enable bit
Set this bit to enable the analog comparator 0 interrupt.
Clear this bit to disable the analog comparator 0 interrupt.
Bit 5, 4– AC0IS1, AC0IS0: Analog Comparator 0 Interrupt Select bit
These 2 bits determine the sensitivity of the interrupt trigger.
The different setting are shown in Table 20-1.
Bit 3 – ACCKSEL: Analog Comparator Clock Select
Set this bit to use the PLL output as comparator clock.
Clear this bit to use the CLK
IO
as comparator clock.
Bit 2, 1, 0– AC0M2, AC0M1, AC0M0: Analog Comparator 0 Multiplexer register
These 3 bits determine the input of the negative input of the analog comparator.
The different setting are shown in Table 20-2.
Bit 76543210
AC0EN AC0IE AC0IS1 AC0IS0 ACCKSEL AC0M2 AC0M1 AC0M0 AC0CON
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 20-1. Interrupt sensitivity selection
AC0IS1 AC0IS0 Description
0 0 Comparator Interrupt on output toggle
01Reserved
1 0 Comparator interrupt on output falling edge
1 1 Comparator interrupt on output rising edge
Table 20-2. Analog Comparator 0 negative input selection
AC0M2 AC0M1 AC0M0 Description
000“Vref/6.40
001“Vref/3.20
010“Vref/2.13
011“Vref/1.60
100Bandgap (1.1V)
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