Rainbow-electronics ATmega64C1 Manual de usuario descargar pdf (Pagina 148)

100

101

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7647A–AVR–02/08

ATmega32/64/M1/C1

14.12 Analog Synchronization

Each PSC module generates a signal to synchronize the ADC sample and hold; synchronisation

is mandatory for measurements.

This signal can be selected between all falling or rising edge of PSCOUTnA or PSCOUTnB

outputs.

In center aligned mode, OCRnRAH/L is not used, so it can be used to specified the synchroniza-

tion of the ADC. It this case, it’s minimum value is 1.

14.13 Interrupt Handling

As each PSC module can be dedicated for one function, each PSC has its own interrupt system

(vector ...)

List of interrupt sources:

• Counter reload (end of On Time 1)

• PSC Input event (active edge or at the beginning of level configured event)

• PSC Mutual Synchronization Error

14.14 PSC Clock Sources

Each PSC has two clock inputs:

• CLK PLL from the PLL

• CLK I/O

Figure 14-14. Clock selection

PCLKSELn bit in PSC Control Register (PCTL) is used to select the clock source.

PPREn1/0 bits in PSC Control Register (PCTL) are used to select the divide factor of the clock.

Table 14-6. Output Clock versus Selection and Prescaler

PCLKSELn PPREn1 PPREn0 CLKPSCn output

000CLK I/O

0 0 1 CLK I/O / 4

0 1 0 CLK I/O / 32

CLK

PSCn

CLK

PLL

I/O

CK/4

CK/32

CK/256

PRESCALER

PPREn1/0

PCLKSEL

1 2 ... 143 144 145 146 147 148 149 150 151 152 153 ... 365 366

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