
ATmega163(L)
103
Figure 64. PORTB Schematic Diagram (Pins PB0 and PB1)
Figure 65. PORTB Schematic Diagram (Pins PB2 and PB3)
2
PUD
PUD: PULL-UP DISABLE
DATA BUS
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
MOS
PULL-
UP
PBn
AINm
TO COMPARATOR
WP:
WD:
RL:
RP:
RD:
n:
m:
WRITE PORTB
WRITE DDRB
READ PORTB LATCH
READ PORTB PIN
READ DDRB
2, 3
0, 1
PWRDN
DDBn
PORTBn
RL
RP
PUD
PUD: PULL-UP DISABLE
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