Rainbow-electronics ATmega103L Manual de usuario descargar pdf (Pagina 28)

ATmega603/103

28

Figure 25. MCU Start-Up, RESET

Controlled Externally

External Reset

An external reset is generated by a low level on the RESET

pin. Reset pulses longer than 50 ns will generate a reset, even

if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the

Reset Threshold Voltage - V

RST

- on its positive edge, the delay timer starts the MCU after the Time-out period t

TOUT

has

expired.

Figure 26. External Reset During Operation

Watchdog Reset

When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle duration. On the falling edge of this

pulse, the delay timer starts counting the Time-out period t

TOUT

. Refer to page 51 for details on operation of the Watchdog.

VCC

RESET

TIME-OUT

INTERNAL

RESET

t

TOUT

V

POT

V

RST

VCC

RESET

TIME-OUT

INTERNAL

RESET

t

TOUT

V

RST

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