Rainbow-electronics AT89C5132 Manual de usuario descargar pdf (Pagina 125)

125

AT8xC5132

4173A–8051–08/02

Master Mode with Interrupt

Policy

Figure 102 shows the initialization phase and the transfer phase flows using the inter-

rupt policy. Using this flow prevents any overrun error occurrence.

• The bit rate is selected according to Table 113.

• The transfer format depends on the slave peripheral.

• SS

may be deasserted between transfers depending also on the slave peripheral.

Reading SPSTA at the beginning of the ISR is mandatory for clearing the SPIF flag.

Clear is effective when reading SPDAT.

Figure 102. Master SPI Interrupt Policy Flows

SPI Initialization

Interrupt Policy

Enable Interrupt

ESPI =1

SPI Interrupt

Service Routine

Select Master Mode

MSTR = 1

Select Bit Rate

Program SPR2:0

Select Format

Program CPOL & CPHA

Enable SPI

SPEN = 1

Read Status

Read SPSTA

Start New Transfer

Write Data in SPDAT

Last Transfer?

Get Data Received

Read SPDAT

Disable Interrupt

SPIE = 0

Select Slave

Pn.x = L

Start Transfer

Write Data in SPDAT

Deselect Slave

Pn.x = H

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