
93
T89C51AC2
Rev. B – 19-Dec-01
Table 56. IPH1 Register
IPH1 (S:FFh)
Interrupt high priority Register 1
Reset Value = XXXX X000b
76543210
- - - - - PADCH -
Bit
Number
Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1 PADCH
ADC Interrupt Priority level most significant bit
PADCH
PADCL Priority level
00Lowest
01
10
11Highest
Comentarios a estos manuales