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T89C51AC2
Rev. B – 19-Dec-01
Table 54. IPL1 Register
IPL1 (S:F8h)
Interrupt Priority Low Register 1
Reset Value: XXXX X000b
bit addressable
76543210
- - - - - PADCL -
Bit
Number
Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1 PADCL
ADC Interrupt Priority level less significant bit.
Refer to PSPIH for priority level.
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