39
3538A–MICRO–7/06
AT89LP213/214 [Preliminary]
bit and prepares to receive the data bytes that follows. The slaves that are not addressed set
their SM2 bits and ignore the data bytes.
The SM2 bit has no effect in Mode 0 but can be used to check the validity of the stop bit in
Mode 1. In a Mode 1 reception, if SM2 = 1, the receive interrupt is not activated unless a valid
stop bit is received.
Notes: 1. SMOD0 is located at PCON.6.
2. f
osc
= oscillator frequency.
Table 17-1. SCON – Serial Port Control Register
SCON Address = 98H Reset Value = 0000 0000B
Bit Addressable
SM0/FE SM1 SM2 REN TB8 RB8 T1 RI
Bit7 6543210
(SMOD0 = 0/1)
(1)
Symbol Function
FE
Framing error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid
frames and must be cleared by software. The SMOD0 bit must be set to enable access to the FE bit. FE will be set
regardless of the state of SMOD0.
SM0 Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)
SM1
Serial Port Mode Bit 1
SM2
Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the received
9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. In Mode 1, if SM2 =
1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a Given or Broadcast
Address. In Mode 0, SM2 should be 0.
REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
RB8
In Modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. In Mode
0, RB8 is not used.
TI
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the
other modes, in any serial transmission. Must be cleared by software.
RI
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the
other modes, in any serial reception (except see SM2). Must be cleared by software.
SM0 SM1 Mode Description Baud Rate
(2)
0 0 0 shift register f
osc
/2
0 1 1 8-bit UART variable (Timer 1)
1 0 2 9-bit UART f
osc
/32 or f
osc
/16
1 1 3 9-bit UART variable (Timer 1)
(11 paginas)
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