27
11050A–PMAAC–07-Apr-10
AT73C246
(V
DDC
= 1.8V) is started. During this PMU reset, the ‘LED’ pin is driven to VINSYS (LED is
OFF).
• When V
DDC
is ready and V
INSYS
> 2.7V, the internal reset signals previously mentioned are
released, thus enabling the PMU digital core functions.
• Before starting the LDO5 (RTC supply), V
BACKUP
voltage is monitored and if it is lower than
1.8V, the RTC function is resetted. In case of V
BACKUP
> 1.8V, no reset is issued on the RTC
function.
• At this step, the power manager is placed in POWERDOWN state.
11.3 Power Manager Conditional Transitions
11.3.1 POWER-ON EVENTS
POWER-ON EVENTS are validated if all these listed conditions are true:
•V
INSYS
> 3.1V
• AT73C246 internal junction temperature Tj < 110°C
• PWREN pin is high for more than 100ms (see Table 11-1 on page 28).
Note: PWREN pin, with internal 100k pull-down resistor, is active high (V
BACKUP
level). It is possible to
hard wire the PWREN pin to V
BACKUP
to always activate RUN state when V
INSYS
> 3.1V. Conse-
quently, using the software POWER-OFF EVENT (described in Section 11.3.2) will lead to going
back to the RUN state just after the POWERDOWN STATE.
11.3.2 POWER-OFF EVENTS
POWER-OFF EVENTS are validated if one of these listed conditions is true:
•V
INSYS
< 2.9V.
• PWREN pin goes from low to high state and high state is held for more than 5s (see Table
11-1 on page 28).
• Software request: bit 0 (OFF) of register 0x00 (PMU_MODES) is written to 1.
11.3.3 POWER-FAIL EVENTS
POWER-FAIL EVENTS are validated if one of these listed conditions is true:
• AT73C246 internal junction temperature Tj > 130°C
• Any internal power fail detection signal coming from any CPU power supply (V
DD0
, V
DD1
,
V
DD2
, V
DD3
) goes from low to high level.
Note: In case of PWREN pin hard wired high (V
BACKUP
level), the POWER-FAIL EVENTS will lead to the
POWERDOWN state without possibility to go to the RUN state. The power manager will be able to
reach the RUN state only after an HRST event. This prevents the power manager from oscillating
between RUN and POWERDOWN states in case of permanent failure on CPU supplies.
11.3.4 STANDBY EVENT
STANDBY EVENT is validated if the following condition is true:
• Software request: bit 1 (STANDBY) of register 0x00 (PMU_MODES) is written to 1.
11.3.5 STANDBY-OUT EVENT
STANDBY-OUT EVENT is validated if the following condition is true:
•V
INSYS
< 2.9V.
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