
DS1215
032697 10/15
TIMING DIAGRAM: READ CYCLE TO TIME CHIP ROM/RAM = GND
CEI
OE
Q
WE
= V
IH
OUTPUT DATA VALID
t
RC
t
OD
t
RR
t
CO
t
OE
t
COE
t
ODO
t
OEE
TIMING DIAGRAM: WRITE CYCLE TO TIME CHIP ROM/RAM = GND
WE
CEI
D
OE
= V
IH
DATA IN STABLE
t
DS
t
DH
t
DH
t
CW
t
WR
t
WR
t
WP
t
WC
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