Rainbow-electronics AT45DB161D Manual de usuario descargar pdf (Pagina 4)

3500O–DFLASH–11/2012

AT45DB161D

3. Block Diagram

4. Memory Array

To provide optimal flexibility, the memory array of the AT45DB161D is divided into three levels of granularity

comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illustrates the breakdown of each

level and details the number of pages per sector and block. All program operations to the DataFlash occur on a

page by page basis. The erase operations can be performed at the chip, sector, block or page level.

Figure 4-1. Memory Architecture Diagram

FLASH MEMORY ARRAY

PAGE (512-/528-BYTES)

BUFFER 2 (512-/528-BYTES)BUFFER 1 (512-/528-BYTES)

I/O INTERFACE

SCK

RESET

VCC

GND

RDY/BUSY

SO SI

SECTOR 0a = 8 Pages

4,096-/4,224-bytes

SECTOR 0b = 248 Pages

126,976-/130,944-bytes

Block = 4,096-/4,224-bytes

8 Pages

SECTOR 0

SECTOR 1

Page = 512-/528-bytes

PAGE 0

PAGE 1

PAGE 6

PAGE 7

PAGE 8

PAGE 9

PAGE 4,094

PAGE 4,095

BLOCK 0

PAGE 14

PAGE 15

PAGE 16

PAGE 17

PAGE 18

BLOCK 1

SECTOR ARCHITECTURE BLOCK ARCHITECTURE PAGE ARCHITECTURE

BLOCK 0

BLOCK 1

BLOCK 30

BLOCK 31

BLOCK 32

BLOCK 33

BLOCK 510

BLOCK 511

BLOCK 62

BLOCK 63

BLOCK 64

BLOCK 65

SECTOR 2

SECTOR 15 = 256 Pages

131,072-/135,168-bytes

BLOCK 2

SECTOR 1 = 256 Pages

131,072-/135,168-bytes

SECTOR 14 = 256 Pages

131,072-/135,168-bytes

SECTOR 2 = 256 Pages

131,072-/135,168-bytes

1 2 3 4 5 6 7 8 9 ... 50 51

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