Rainbow-electronics AT25DF081A Manual de usuario

Features• Single 2.7V - 3.6V Supply• Serial Peripheral Interface (SPI) Compatible– Supports SPI Modes 0 and 3– Supports RapidS™Operation– Supports Dua

108715C–SFLSH–11/2012AT25DF081A7.2 Dual-Output Read ArrayThe Dual-Output Read Array command is similar to the standard Read Array command and can be u

118715C–SFLSH–11/2012AT25DF081A8. Program and Erase Commands8.1 Byte/Page ProgramThe Byte/Page Program command allows anywhere from a single byte of d

128715C–SFLSH–11/2012AT25DF081AFigure 8-1. Byte ProgramFigure 8-2. Page ProgramSCKCSSISOMSB MSB231000000010675410119812 3937 3833 36353431 3229 30OPCO

138715C–SFLSH–11/2012AT25DF081A8.2 Dual-Input Byte/Page ProgramThe Dual-Input Byte/Page Program command is similar to the standard Byte/Page Program c

148715C–SFLSH–11/2012AT25DF081AFigure 8-3. Dual-Input Byte ProgramFigure 8-4. Dual-Input Page ProgramSCKCSSISOIMSB MSB231010100010675410119812 3335343

158715C–SFLSH–11/2012AT25DF081A8.3 Block EraseA block of 4-, 32-, or 64-Kbytes can be erased (all bits set to the logical “1” state) in a single opera

168715C–SFLSH–11/2012AT25DF081A8.4 Chip EraseThe entire memory array can be erased in a single operation by using the Chip Erase command. Before a Chi

178715C–SFLSH–11/2012AT25DF081A9. Protection Commands and Features9.1 Write EnableThe Write Enable command is used to set the Write Enable Latch (WEL)

188715C–SFLSH–11/2012AT25DF081A9.2 Write DisableThe Write Disable command is used to reset the Write Enable Latch (WEL) bit in the Status Register to

198715C–SFLSH–11/2012AT25DF081A9.3 Protect SectorEvery physical 64-Kbyte sector of the device has a corresponding single-bit Sector Protection Registe

28715C–SFLSH–11/2012AT25DF081A1. DescriptionThe Adesto®AT25DF081A is a serial interface Flash memory device designed for use in a wide variety of high

208715C–SFLSH–11/2012AT25DF081A9.4 Unprotect SectorIssuing the Unprotect Sector command to a particular sector address will reset the corresponding Se

218715C–SFLSH–11/2012AT25DF081A9.5 Global Protect/UnprotectThe Global Protect and Global Unprotect features can work in conjunction with the Protect S

228715C–SFLSH–11/2012AT25DF081AEssentially, if the SPRL bit of the Status Register is in the logical “0” state (Sector Protection Registers are notloc

238715C–SFLSH–11/2012AT25DF081A9.6 Read Sector Protection RegistersThe Sector Protection Registers can be read to determine the current software prote

248715C–SFLSH–11/2012AT25DF081A9.7 Protected States and the Write Protect (WP) PinThe WP pin is not linked to the memory array itself and has no direc

258715C–SFLSH–11/2012AT25DF081A10. Security Commands10.1 Sector LockdownCertain applications require that portions of the Flash memory array be perman

268715C–SFLSH–11/2012AT25DF081AFigure 10-1. Sector Lockdown10.2 Freeze Sector Lockdown StateThe current sector lockdown state can be permanently froze

278715C–SFLSH–11/2012AT25DF081A10.3 Read Sector Lockdown RegistersThe Sector Lockdown Registers can be read to determine the current lockdown status o

288715C–SFLSH–11/2012AT25DF081A10.4 Program OTP Security RegisterThe device contains a specialized OTP (One-Time Programmable) Security Register that

298715C–SFLSH–11/2012AT25DF081AThe three address bytes and at least one complete byte of data must be clocked into the device before the CS pinis deas

38715C–SFLSH–11/2012AT25DF081A2. Pin Descriptions and PinoutsTable 2-1. Pin DescriptionsSymbol Name and FunctionAssertedState TypeCSCHIP SELECT: Asser

308715C–SFLSH–11/2012AT25DF081A10.5 Read OTP Security RegisterThe OTP Security Register can be sequentially read in a similar fashion to the Read Arra

318715C–SFLSH–11/2012AT25DF081A11. Status Register Commands11.1 Read Status RegisterThe two-byte Status Register can be read to determine the device’s

328715C–SFLSH–11/2012AT25DF081ANotes: 1. Only bits 4 and 3 of Status Register Byte 2 will be modified when using the Write Status Register Byte 2 comm

338715C–SFLSH–11/2012AT25DF081A11.1.3 WPP BitThe WPP bit can be read to determine if theWP pin has been asserted or not.11.1.4 SWP BitsThe SWP bits pr

348715C–SFLSH–11/2012AT25DF081A11.1.7 SLE BitThe SLE bit is used to enable and disable the Sector Lockdown and Freeze Sector Lockdown State commands.W

358715C–SFLSH–11/2012AT25DF081A11.2 Write Status Register Byte 1The Write Status Register Byte 1 command is used to modify the SPRL bit of the Status

368715C–SFLSH–11/2012AT25DF081A11.3 Write Status Register Byte 2The Write Status Register Byte 2 command is used to modify the RSTE and SLE bits of th

378715C–SFLSH–11/2012AT25DF081A12. Other Commands and Functions12.1 ResetIn some applications, it may be necessary to prematurely terminate a program

388715C–SFLSH–11/2012AT25DF081A12.2 Read Manufacturer and Device IDIdentification information can be read from the device to enable systems to electro

398715C–SFLSH–11/2012AT25DF081AFigure 12-2. Read Manufacturer and Device ID12.3 Deep Power-DownDuring normal operation, the device will be placed in t

48715C–SFLSH–11/2012AT25DF081A3. Block DiagramFigure 3-1. Block DiagramVCCDEVICE POWER SUPPLY: The VCCpin is used to supply the source voltage to the

408715C–SFLSH–11/2012AT25DF081AFigure 12-3. Deep Power-Down12.4 Resume from Deep Power-DownIn order to exit the Deep Power-Down mode and resume normal

418715C–SFLSH–11/2012AT25DF081A12.5 HoldThe HOLD pin is used to pause the serial communication with the device without having to stop or reset the clo

428715C–SFLSH–11/2012AT25DF081A13. RapidS ImplementationTo implement RapidS and operate at clock frequencies higher than what can be achieved in a via

438715C–SFLSH–11/2012AT25DF081A14. Electrical Specifications14.1 Absolute Maximum Ratings*14.2 DC and AC Operating Range14.3 DC CharacteristicsTempera

448715C–SFLSH–11/2012AT25DF081A14.4 AC Characteristics – Maximum Clock Frequencies14.5 AC Characteristics – All Other ParametersNotes: 1. Not 100% tes

458715C–SFLSH–11/2012AT25DF081A14.6 Program and Erase CharacteristicsNotes: 1. Maximum values indicate worst-case performance after 100,000 erase/prog

468715C–SFLSH–11/2012AT25DF081A15. AC WaveformsFigure 15-1. Serial Input TimingFigure 15-2. Serial Output TimingFigure 15-3.WP Timing for Write Status

478715C–SFLSH–11/2012AT25DF081AFigure 15-4. HOLD Timing – Serial InputFigure 15-5. HOLD Timing – Serial OutputCSSISCKSOtHHHtHLStHLHtHHSHOLDHIGH-IMPEDA

488715C–SFLSH–11/2012AT25DF081A16. Ordering Information16.1 Code Detail Detail16.2 Green Package Options (Pb/Halide-free/RoHS Compliant)Note: The ship

498715C–SFLSH–11/2012AT25DF081A17. Packaging Information17.1 8MA1 – UDFNTITLEDRAWING NO.GPCREV.Package Drawing Contact:[email protected] YFG

58715C–SFLSH–11/2012AT25DF081A4. Memory ArrayTo provide the greatest flexibility, the memory array of the AT25DF081A can be erased in four levels of g

508715C–SFLSH–11/2012AT25DF081A17.2 8S1 – JEDEC SOICDRAWING NO. REV. TITLE GPCCOMMON DIMENSIONS(Unit of Measure = mm)SYMBOLMINNOMMAXNOTE A1 0.10 –

518715C–SFLSH–11/2012AT25DF081A17.3 8S2 – EIAJ SOICTITLEDRAWING NO. GPCREV.Package Drawing Contact:[email protected] STN F 8S2, 8-lead, 0.2

528715C–SFLSH–11/2012AT25DF081A18. Revision HistoryDoc. Rev. Date Comments8715C 11/2012 Update to Adesto logos.8715B 08/2010 Change tRDPDMax from 10 t

Corporate OfficeCalifornia | USAAdesto Headquarters1250 Borregas AvenueSunnyvale, CA 94089 Phone: (+1) 408.400.0578Email: [email protected]© 2012

68715C–SFLSH–11/2012AT25DF081A5. Device OperationThe AT25DF081A is controlled by a set of instructions that are sent from a host controller, commonly

78715C–SFLSH–11/2012AT25DF081ATable 6-1. Command ListingCommand OpcodeClockFrequencyAddressBytesDummyBytesDataBytesRead CommandsRead Array1Bh 0001 101

88715C–SFLSH–11/2012AT25DF081A7. Read Commands7.1 Read ArrayThe Read Array command can be used to sequentially read a continuous stream of data from t

98715C–SFLSH–11/2012AT25DF081AFigure 7-2. Read Array – 0Bh OpcodeFigure 7-3. Read Array – 03h OpcodeSCKCSSISOMSB MSB231000001011675410119812 394243414