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DRAFT

Features

• Master and Slave Operation Possible

• Supply Voltage up to 40V

• Operating voltage V

= 5V to 27V

• Typically 10 µA Supply Current During Sleep Mode

• Typically 57 µA Supply Current in Silent Mode

• Linear Low-drop Voltage Regulator:

– Normal, Fail-safe, and Silent Mode

– ATA6622 V

= 3.3V ±2%

– ATA6624 V

= 5.0V ±2%

– ATA6626 V

= 5.0V ±2%, TXD Time-out Timer Disabled

– In Sleep Mode V

is Switched Off

• VCC- Undervoltage Detection (4 ms Reset Time) and Watchdog Reset Logical

Combined at Open Drain Output NRES

• Negative Trigger Input for Watchdog

• Boosting the Voltage Regulator Possible with an External NPN Transistor

• LIN Physical Layer According to LIN 2.0 Specification and SAEJ2602-2

• Wake-up Capability via LIN-bus, Wake Pin, or Kl_15 Pin

• INH Output to Control an External Voltage Regulator or to Switch off the Master Pull Up

Resistor

• TXD Time-out Timer; ATA6626 TXD Time-out Timer Is Disabled

• Bus Pin is Overtemperature and Short Circuit Protected versus GND and Battery

• Adjustable Watchdog Time via External Resistor

• Advanced EMC and ESD Performance

• ESD HBM 8 kV at Pins LIN and VS According to STM5.1

• Package: QFN 5 mm × 5 mm with 20 Pins

1. Description

The ATA6622 is a fully integrated LIN transceiver, which complies with the LIN 2.0

and SAEJ2602-2 specifications. It has a low-drop voltage regulator for 3.3V/50 mA

output and a window watchdog. The ATA6624 has the same functionality as the

ATA6622; however, it uses a 5V/50 mA regulator. The ATA6626 has the same func-

tionality as ATA6624 without a TXD time-out timer. The voltage regulator is able to

source 50 mA up to V

= 18V. The output current of the regulator can be boosted by

using an external NPN transistor. This chip combination makes it possible to develop

inexpensive, simple, yet powerful slave and master nodes for LIN-bus systems.

ATA6622/ATA6624/ATA6626 are designed to handle the low-speed data communica-

tion in vehicles, e.g., in convenience electronics. Improved slope control at the

LIN-driver ensures secure data communication up to 20 kBaud. Sleep Mode and

Silent Mode guarantee very low current consumption. The ATA6626 is able to switch

the LIN unlimited to dominant level via TXD for low data rates.

LIN Bus

Transceiver

with 3.3V (5V)

Regulator and

Watchdog

ATA6622

ATA6624

ATA6626

Preliminary

4986B–AUTO–07/07

1 2 3 4 5 6 ... 27 28

Indice de contenidos

Pagina 1 - 1. Description

DRAFTFeatures• Master and Slave Operation Possible• Supply Voltage up to 40V• Operating voltage VS = 5V to 27V• Typically 10 µA Supply Current During

Pagina 2 - Figure 1-1. Block Diagram

104986B–AUTO–07/07ATA6622/ATA6624/ATA6626 [Preliminary] DRAFTThe VCC regulator is activated, and the internal LIN slave termination resistor is switch

Pagina 3 - 2. Pin Configuration

114986B–AUTO–07/07ATA6622/ATA6624/ATA6626 [Preliminary]DRAFTFigure 4-5. LIN Wake Up from Sleep Mode Table 4-1. Table of ModesMode of Operation Transce

Pagina 4 - 3. Functional Description

124986B–AUTO–07/07ATA6622/ATA6624/ATA6626 [Preliminary] DRAFT5. Wake-up Scenarios from Silent or Sleep Mode5.1 Remote Wake-up via Dominant Bus StateA

Pagina 5

134986B–AUTO–07/07ATA6622/ATA6624/ATA6626 [Preliminary]DRAFT5.5 Fail-safe Features• During a short-circuit at LIN to VBattery, the output limits the o

Pagina 6

144986B–AUTO–07/07ATA6622/ATA6624/ATA6626 [Preliminary] DRAFTFigure 5-1. VCC Voltage Regulator: Ramp-up and Undervoltage Detection Figure 5-2. Power D

Pagina 7 - 4. Modes of Operation

154986B–AUTO–07/07ATA6622/ATA6624/ATA6626 [Preliminary]DRAFT6. WatchdogThe watchdog anticipates a trigger signal from the microcontroller at the NTRIG

Pagina 8

164986B–AUTO–07/07ATA6622/ATA6624/ATA6626 [Preliminary] DRAFTFigure 6-1. Timing Sequence with RWD_OSC = 51 kΩ 6.2 Worst Case Calculation with RWD_OSC

Pagina 9 - 4.3 Sleep Mode

174986B–AUTO–07/07ATA6622/ATA6624/ATA6626 [Preliminary]DRAFT7. Absolute Maximum RatingsStresses beyond those listed under “Absolute Maximum Ratings” m

Pagina 10 - 4.5 Unpowered Mode

184986B–AUTO–07/07ATA6622/ATA6624/ATA6626 [Preliminary] DRAFT8. Electrical Characteristics5V < VS < 27V, -40°C < Tj < 150°C, unless otherw

Pagina 11 - Table 4-1. Table of Modes

194986B–AUTO–07/07ATA6622/ATA6624/ATA6626 [Preliminary]DRAFT4EN Input Pin4.1 Low-level voltage input EN VENL–0.3 +0.8 V A4.2 High-level voltage input

Pagina 12

24986B–AUTO–07/07ATA6622/ATA6624/ATA6626 [Preliminary] DRAFTFigure 1-1. Block Diagram AdjustableWatchdogOscillatorShort Circuit andOvertemperatureProt

Pagina 13 - 5.6 Voltage Regulator

204986B–AUTO–07/07ATA6622/ATA6624/ATA6626 [Preliminary] DRAFT8.8Input leakage current at the receiver including pull-up resistor as specifiedInput lea

Pagina 14 - 4986B–AUTO–07/07

214986B–AUTO–07/07ATA6622/ATA6624/ATA6626 [Preliminary]DRAFT10.6 Duty cycle 1THRec(max) = 0.744 × VSTHDom(max) = 0.581 × VSVS = 7.0V to 18VtBit = 50 µ

Pagina 15 - 6. Watchdog

224986B–AUTO–07/07ATA6622/ATA6624/ATA6626 [Preliminary] DRAFT13 Watchdog Oscillator13.1Voltage at WD_OSC in Normal ModeIWD_OSC = –200 µAVVS ≥ 4VVWD_OS

Pagina 16 - = 51 kΩ

234986B–AUTO–07/07ATA6622/ATA6624/ATA6626 [Preliminary]DRAFT17 VCC Voltage Regulator ATA662217.1 Output voltage VCC4V < VS < 18V(0 mA to 50 mA)V

Pagina 17 - 7. Absolute Maximum Ratings

244986B–AUTO–07/07ATA6622/ATA6624/ATA6626 [Preliminary] DRAFTFigure 8-1. Definition of Bus Timing Characteristics TXD(Input to transmitting node)VS(Tr

Pagina 18 - 8. Electrical Characteristics

254986B–AUTO–07/07ATA6622/ATA6624/ATA6626 [Preliminary]DRAFTFigure 8-2. Application Circuit 67 8 10920 19 18MLP 5 mm × 5 mm0.65 mm pitch20 leadATA6622

Pagina 19

264986B–AUTO–07/07ATA6622/ATA6624/ATA6626 [Preliminary] DRAFT10. Package Information9. Ordering InformationExtended Type Number Package RemarksATA6622

Pagina 20

274986B–AUTO–07/07ATA6622/ATA6624/ATA6626 [Preliminary]DRAFT11. Revision HistoryPlease note that the following page numbers referred to in this sectio

Pagina 21 - Figure 8-1 on

4986B–AUTO–07/07DRAFTHeadquarters InternationalAtmel Corporation2325 Orchard ParkwaySan Jose, CA 95131USATel: 1(408) 441-0311Fax: 1(408) 487-2600Atmel

Pagina 22

34986B–AUTO–07/07ATA6622/ATA6624/ATA6626 [Preliminary]DRAFT2. Pin ConfigurationFigure 2-1. Pinning SO8 67 8 10920 19 18QFN 5 mm × 5 mm0.65 mm pitch20

Pagina 23

44986B–AUTO–07/07ATA6622/ATA6624/ATA6626 [Preliminary] DRAFT3. Functional Description3.1 Physical Layer CompatibilitySince the LIN physical layer is i

Pagina 24

54986B–AUTO–07/07ATA6622/ATA6624/ATA6626 [Preliminary]DRAFT3.7 Input/Output Pin (TXD)In Normal Mode the TXD pin is the microcontroller interface used

Pagina 25 - Microcontroller

64986B–AUTO–07/07ATA6622/ATA6624/ATA6626 [Preliminary] DRAFT3.13 TM Input PinThe TM pin is used for final production measurements at Atmel®. In normal

Pagina 26

74986B–AUTO–07/07ATA6622/ATA6624/ATA6626 [Preliminary]DRAFT4. Modes of OperationFigure 4-1. Modes of Operation 4.1 Normal ModeThis is the normal trans

Pagina 27 - 11. Revision History

84986B–AUTO–07/07ATA6622/ATA6624/ATA6626 [Preliminary] DRAFTA voltage less than the LIN Pre_Wake detection VLINL at the LIN pin activates the internal

Pagina 28 - Product Contact

94986B–AUTO–07/07ATA6622/ATA6624/ATA6626 [Preliminary]DRAFTFigure 4-3. LIN Wake Up from Silent Mode 4.3 Sleep ModeA falling edge at EN when TXD is low

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