
10
AT77C101B
2150A–BIOM–02/02
.
Table 7. Switching Performances. T
amb
= 25°C; F
PCLK
= 1 MHz; Duty cycle = 50%
C
load
120 pF on digital and analog outputs unless otherwise specified
Parameter Symbol Test Level Min Typ Max Unit
Clock frequency f
PCLK
I0.512MHz
Clock pulse width (high) t
HCLK
I250 ns
Clock pulse width (low) t
LCLK
I250 ns
Clock setup time (high)/reset falling edge t
Setup
I0ns
No data change t
NOOE
IV 100 ns
Reset pulse width high t
HRST
IV 50 ns
Table 8. 5.0V All Power Supplies = +5V
Parameter Symbol Test Level Min Typ Max Unit
Output delay from PCLK to ACKN rising edge t
PLHACKN
I90ns
Output delay from PCLK to ACKN falling edge t
PHLACKN
I85ns
Output delay from PCLK to Data output Dxi t
PDATA
I75ns
Output delay from PCLK to Analog output Avx t
PAV I D EO
I 260 ns
Output delay from OE to data high-Z t
DATAZ
IV 25 ns
Output delay from OE to data output t
ZDATA
IV 29 ns
Table 9. 3.3V All Power Supplies = +3.3V
Parameter Symbol Test Level Min Typ Max Unit
Output delay from PCLK to ACKN rising edge t
PLHACKN
I 110 ns
Output delay from PCLK to ACKN falling edge t
PHLACKN
I 100 ns
Output delay from PCLK to Data output Dxi t
PDATA
I90ns
Output delay from PCLK to Analog output AVx t
PAV ID E O
I 250 ns
Output delay from OE to data high-Z t
DATAZ
IV 34 ns
Output delay from OE to data output t
ZDATA
IV 47 ns
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