Rainbow-electronics ATF1504ASVL Manual de usuario descargar pdf (Pagina 8)

ATF1504ASV(L)

1409H–PLD–09/02

Input Diagram

I/O Diagram

Speed/Power

Management

The ATF1504ASV(L) has several built-in speed and power management features. The

ATF1504ASV(L) contains circuitry that automatically puts the device into a low power

standby mode when no logic transitions are occurring. This not only reducespower con-

sumption during inactive periods, but also provides proportional powersavings for most

applications running at systemspeeds below 5 MHz. This feature may be selectedasa

device option.

To furtherreduce power, each ATF1504ASV(L)macrocell has a reduced-powerbitfea-

ture. This feature allows individual macrocells to be configured for maximum power

savings. This feature may be selectedasadesign option.

All ATF1504ASV(L)alsohave an optional power-down mode. In this mode,current

drops to below 5 mA. Whenthe power-down option is selected, either PD1 or PD2 pins

(or both) can be usedtopower down the part. The power-down option is selectedinthe

design source file. When enabled, the device goes into power down when either PD1 or

PD2 is high. In the power-down mode, all internal logic signals are latched and held, as

are any enabled outputs.

All pin transitions are ignored until thePDpin is brought low. Whenthe power-down fea-

ture is enabled, thePD1or PD2 pin cannot be used as a logic input or output.However,

the pin’smacrocell may still be usedtogenerate buried foldback and cascade logic

signals.

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