
Preliminary W79E8213/W79E8213R Data Sheet
Publication Release Date: July 11, 2008
- 12 - Revision A2
Bank 0
Bank 1
Bank 2
Bank 3
03 02 01 0004050607
0B 0A 09 080C0D0E0F
13 12 11 1014151617
1B 1A 19 181C1D1E1F
23 22 21 2024252627
2B 2A 29 282C2D2E2F
33
32
31
30
34
353637
3B 3A 39 383C3D3E3F
43 42
41
4044
454647
4B 4A 49 484C4D4E4F
53 52 51 5054555657
5B 5A 59 585C5D5E5F
63 62 61 6064656667
6B 6A 69 686C6D6E6F
73 72 71 7074757677
7B 7A 79 787C7D7E7F
Direct RAM
Indirect RAM
00H
07H
28H
08H
0FH
10H
17H
18H
1FH
20H
21H
22H
23H
24H
25H
26H
27H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
7FH
80H
FFH
Figure 7-3: Scratch pad RAM
7.4.1 Working Registers
There are four sets of working registers, each consisting of eight 8-bit registers. These are termed as
Banks 0, 1, 2, and 3. Individual registers within these banks can be directly accessed by separate
instructions. These individual registers are named as R0, R1, R2, R3, R4, R5, R6 and R7. However, at
one time the W79E8213 series can work with only one particular bank. The bank selection is done by
setting RS1-RS0 bits in the PSW. The R0 and R1 registers are used to store the address for indirect
accessing.
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