Rainbow-electronics T89C51AC2 Manual de usuario descargar pdf (Pagina 38)

T89C51AC2

Rev. B – 19-Dec-01

Figure 15. Reading Procedure

9.3.8 Flash Protection from

Parallel Programming

The three lock bits in Hardware Security Byte (see "In-System Programming" section)

are programmed according to Table 11 provide different level of protection for the on-

chip code and data located in FM0 and FM1.

The only way to write this bits are the parallel mode. They are set by default to level 4

Table 11. Program Lock bit

Program Lock bits

U: unprogrammed

P: programmed

WARNING: Security level 2 and 3 should only be programmed after Flash and Core

verification.

FLASH Spaces

Reading

FLASH Spaces Mapping

FCON= 00000xx0b

Data Read

DPTR= Address

ACC= 0

Exec:MOVCA,@A+DPTR

Clear Mode

FCON = 00h

Program Lock Bits

Protection description

Security

level

LB0 LB1 LB2

1UUU

No program lock features enabled. MOVC instruction executed from

external program memory returns non encrypted data.

2PUU

MOVC instruction executed from external program memory are

disabled from fetching code bytes from internal memory, EA

is sampled

and latched on reset, and further parallel programming of the Flash is

disabled.

3UPU

Same as 2, also verify through parallel programming interface is

disabled.

4 UUP

Same as 3, also external execution is disabled if code roll over beyond

7FFFh

1 2 ... 33 34 35 36 37 38 39 40 41 42 43 ... 109 110

T89C51AC2 1

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