NUC140 Series DATA SHEET
Publication Release Date: May 31, 2010
- 8 - Revision V1.02
• I
2
C
– Two sets of I
2
C device.
– Master/Slave up to 1Mbit/s ( Fast-mode Plus )
– Bidirectional data transfer between masters and slaves
– Multi-master bus (no central master).
– Arbitration between simultaneously transmitting masters without corruption of serial data on
the bus
– Serial clock synchronization allows devices with different bit rates to communicate via one
serial bus.
– Serial clock synchronization can be used as a handshake mechanism to suspend and resume
serial transfer.
– Programmable clocks allow versatile rate control.
– I2C-bus controllers support multiple address recognition ( two slave address with mask option)
• I
2
S
– Interface with external audio CODEC
– Operate as either master or slave mode
– Capable of handling 8, 16, and 32 bit word sizes
– Mono and stereo audio data supported
– I
2
S and MSB justified data format supported
– Two 8 word FIFO data buffers are provided, one for transmit and one for receive
– Generates interrupt requests when buffer levels cross a programmable boundary
– Support two DMA requests, one for transmit and one for receive
• CAN 2.0
– CAN 2.0B protocol compatible device
– Support 11-bit identifier as well as 29-bit identifier
– Bit rates up to 1Mbits/s
– NRZ bit Coding/ Encoding
– Error Detection & Status Report
Bit error, Form error, Stuffing error, 15-bit CRC detection, and Acknowledge error
Interrupt
Each CAN-bus error, and Transmission/Receive Done.
– Bit Timing Synchronization
– Acceptance filter extension
– Sleep mode wake up
• USB 2.0 Full-Speed Device
– One set of USB 2.0 FS Device 12Mbps
– On-chip USB Transceiver.
– Provide 1 interrupt source with 4 interrupt events.
– Support Control, Bulk In/Out, Interrupt and Isochronous transfers.
– Auto suspend function when no bus signaling for 3 ms.
– Provide 6 programmable endpoints.
– Include 512 Bytes internal SRAM as USB buffer.
– Provide remote wakeup capability.
– Support PDMA mode
(40 paginas)
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