Power-Down Lockout Input (PDL)
The power-down lockout pin (PDL) disables shutdown
when low. When in shutdown mode, a high-to-low tran-
sition on PDL will wake up the DAC with its output still
set to the state prior to power-down. PDL can also be
used to wake up the device asynchronously.
Power-Down Input (PD)
Pulling PD high places the MAX5130/MAX5131 in shut-
down mode. Pulling PD low will not return the MAX5130/
MAX5131 to normal operation. A high-to-low transition
on PDL or appropriate commands (Table 1) via the ser-
ial interface are required to exit power-down.
Serial-Interface Configuration
(SPI/QSPI/MICROWIRE/PIC16/PIC17)
The MAX5130/MAX5131 3-wire serial interface is com-
patible with SPI, QSPI, PIC16/PIC17 (Figure 4) and
MICROWIRE (Figure 5) interface standards. The 2-byte-
long serial input word contains three control bits and 13
data bits in MSB-first format (Table 2).
The MAX5130/MAX5131’s digital inputs are double
buffered, which allows the user to:
• Load the input register without updating the DAC
register,
• Update the DAC register with data from the input
register,
• Update the input and DAC registers concurrently.
MAX5130/MAX5131
+3V/+5V, 13-Bit, Serial Voltage-Output DACs
with Internal Reference
______________________________________________________________________________________ 11
Load input register; DAC register unchanged.13-Bit DAC Data0 0
0
1
0
Update DAC register from input register; exit shutdown.XXXXXXXXXXXXX0 1
1
1
0 Simultaneously load input and DAC registers; exit shutdown.13-Bit DAC Data0
UPO goes low (default).XXXXXXXXXXXXX1 0
0
0
1
Mode 1; DOUT clocked out on SCLK’s rising edge.1XXXXXXXXXXXX1 1
1
1
0 UPO goes high.XXXXXXXXXXXXX1
No operation.XXXXXXXXXXXXX0
16-BIT SERIAL WORD
Shutdown DAC (provided PDL = 1).
XXXXXXXXXXXXX1
Mode 0; DOUT clocked out on SCLK’s falling edge (default).00XXXXXXXXXXX1 1 1
C1 C0C2
FUNCTION
D12 ............... D0
Table 1. Serial-Interface Programming Commands
X = Don’t care
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