input voltage don’t exceed the package ratings or violate
the overall thermal budget.
Choose a low-side MOSFET (Q2) that has the lowest
possible R
DS(ON)
, comes in a moderate to small pack-
age (i.e., SO-8), and is reasonably priced. Ensure that
the MAX1710/MAX1711/MAX1712 DL gate driver can
drive Q2; in other words, check that the gate isn’t pulled
up by the high-side switch turning on due to parasitic
drain-to-gate capacitance, causing cross-conduction
problems. Switching losses aren’t an issue for the low-
side MOSFET since it’s a zero-voltage switched device
when used in the buck topology.
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET, the worst-case
power dissipation due to resistance occurs at minimum
battery voltage:
PD(Q1) = (V
OUT
/ V
BATT(MIN)
)
✕
I
LOAD
2
✕
R
DS(ON)
Generally, a small high-side MOSFET is desired in order
to reduce switching losses at high input voltages.
However, the R
DS(ON)
required to stay within package
power-dissipation limits often limits how small the MOS-
FET can be. Again, the optimum occurs when the switch-
ing (AC) losses equal the conduction (R
DS(ON)
) losses.
High-side switching losses don’t usually become an
issue until the input is greater than approximately 15V.
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied, due to the squared term in the
CV
2
F switching loss equation. If the high-side MOSFET
you’ve chosen for adequate R
DS(ON)
at low battery volt-
ages becomes extraordinarily hot when subjected to
V
BATT(MAX)
, you must reconsider your choice of MOS-
FET.
Calculating the power dissipation in Q1 due to switching
losses is difficult, since it must allow for difficult-to-quanti-
MAX1710/MAX1711/MAX1712
High-Speed, Digitally Adjusted
Step-Down Controllers for Notebook CPUs
20 ______________________________________________________________________________________
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