MAX17000
Complete DDR2 and DDR3 Memory
Power-Management Solution
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Detailed Description
The MAX17000 complete DDR solution comprises a
step-down controller, a source-sink LDO regulator, and a
reference buffer. Maxim’s proprietary Quick-PWM pulse-
width modulator in the MAX17000 is specifically
designed for handling fast load steps while maintaining a
relatively constant operating frequency and inductor
operating point over a wide range of input voltages. The
Quick-PWM architecture circumvents the poor load-tran-
sient timing problems of fixed-frequency current-mode
PWMs, while also avoiding the problems caused by
widely varying switching frequencies in conventional con-
stant-on-time and constant-off-time PWM schemes.
Figure 1 is the MAX17000 standard application circuit
and Figure 2 is the MAX17000 functional diagram.
The MAX17000 includes a ±2A source-sink LDO regu-
lator for the memory termination rail. The source-sink
regulator features a dead band that either sources or
sinks, ideal for the fast-changing short-period loads
presenting in memory termination applications. This
feature also reduces the VTT output capacitance
requirement down to 1μF, though load-transient
response can still require higher capacitance values
between 10μF and 20μF.
The reference buffer sources and sinks ±3mA, generating
a reference rail for use in the memory controller and
memory devices.
1. CONNECT FB TO 5V FOR FIXED +1.8V.
2. CONNECT FB TO GND FOR FIXED +1.5V.
3. USE FB RESISTOR-DIVIDER FOR ADJUSTABLE
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