MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
20 ______________________________________________________________________________________
Data Throughput
The data throughput (f
TH
) of the MAX1304–MAX1306/
MAX1308–MAX1310/MAX1312–MAX1314 is a function
of the clock speed (f
CLK
). In internal clock mode, f
CLK
=
15MHz (typ). In external clock mode, 100kHz ≤ f
CLK
≤
20MHz. When reading during conversion (Figures 7 and
8), calculate f
TH
as follows:
where N is the number of active channels and t
QUIET
is
the period of bus inactivity before the rising edge of
CONVST. See the Starting a Conversion section for
more information.
Table 1 uses the above equation and shows the total
throughput as a function of the number of channels
selected for conversion.
Clock Modes
The MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–
MAX1314 provide a 15MHz internal conversion clock.
Alternatively, an external clock can be used.
Internal Clock
Internal clock mode frees the microprocessor from the
burden of running the ADC conversion clock. For inter-
nal clock operation, connect INTCLK/EXTCLK to AV
DD
and connect CLK to DGND. Note that INTCLK/EXTCLK
is referenced to AV
DD
, not DV
DD
.
External Clock
For external clock operation, connect INTCLK/EXTCLK
to AGND and connect an external clock source to CLK.
Note that INTCLK/EXTCLK is referenced to AV
DD
, not
DV
DD
. The external clock frequency can be up to
20MHz. Linearity is not guaranteed with clock frequen-
cies below 100kHz due to droop in the T/H circuits.
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