Rainbow-electronics MAX1303 Manual de usuario

General DescriptionThe MAX1302/MAX1303 multirange, low-power, 16-bit,successive-approximation, analog-to-digital converters(ADCs) operate from a singl

MAX1302/MAX13038-/4-Channel, ±VREFMultirange Inputs, Serial 16-Bit ADCs10 ____________________________________________________________________________

MAX1302/MAX13038-/4-Channel, ±VREFMultirange Inputs, Serial 16-Bit ADCs_______________________________________________________________________________

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MAX1302/MAX13038-/4-Channel, ±VREFMultirange Inputs, Serial 16-Bit ADCs_______________________________________________________________________________

MAX1302/MAX1303Power SuppliesTo maintain a low-noise environment, the MAX1302 andMAX1303 provide separate power supplies for eachsection of circuitry.

As a result, the analog input impedance is relativelyconstant over the input voltage as shown in Figure 5.Single-ended conversions are internally refe

MAX1302/MAX1303Figure 8 illustrates the software-selectable differentialanalog input voltage range that produces a valid digitaloutput. Each analog in

Figure 6. Simplified Analog Input CircuitMAX1302MAX1303R2R1VSJ*RSOURCEANALOGSIGNALSOURCER2R1VSJ*RSOURCEANALOGSIGNALSOURCEIN_+IN_+*MINIMIZE RSOURCE TO

MAX1302/MAX1303Differential Common-Mode RangeThe MAX1302/MAX1303 differential common-moderange (VCMDR) must remain within -4.75V to +5.5V toobtain val

The shaded area contains the valid common-modevoltage ranges that support the entire FSR.Digital InterfaceThe MAX1302/MAX1303 feature a serial interfa

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Start BitCommunication with the MAX1302/MAX1303 is accom-plished using the three input data word formats shownin Table 3. Each input data word begins

MAX1302/MAX1303Mode ControlThe MAX1302/MAX1303 contain one byte-wide mode-control register. The timing diagram of Figure 15 showshow to use the mode-c

• User supplies one byte of SCLK, then drives CShigh to relieve processor load while the ADCconverts• After SSTRB transitions high, the user suppliest

MAX1302/MAX1303External Acquisition Mode (Mode 1)The slowest maximum throughput rate is achieved withthe external acquisition method. SCLK controls th

• External-acquisition-mode control byte• Internal-clock-mode control byte• Reset byte• Partial power-down-mode control byteThis prevents the MAX1302/

MAX1302/MAX1303Bridge ApplicationThe MAX1302/MAX1303 convert 1kHz signals moreaccurately than a similar sigma-delta converter thatmight be considered

Differential Nonlinearity (DNL)DNL is the difference between an actual step width andthe ideal value of 1 LSB. A DNL error specification ofgreater tha

MAX1302/MAX1303Unipolar Offset Error-FSR to 0VWhen a zero-scale analog input voltage is applied tothe converter inputs, the digital output is all ones

Effective Number of Bits (ENOB)ENOB indicates the global accuracy of an ADC at aspecific input frequency and sampling rate. With aninput range equal t

MAX1302/MAX13038-/4-Channel, ±VREFMultirange Inputs, Serial 16-Bit ADCs_______________________________________________________________________________

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MAX1302/MAX13038-/4-Channel, ±VREFMultirange Inputs, Serial 16-Bit ADCsMaxim cannot assume responsibility for use of any circuitry other than circuitr

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MAX1302/MAX13038-/4-Channel, ±VREFMultirange Inputs, Serial 16-Bit ADCs_______________________________________________________________________________

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MAX1302/MAX13038-/4-Channel, ±VREFMultirange Inputs, Serial 16-Bit ADCs_______________________________________________________________________________

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MAX1302/MAX13038-/4-Channel, ±VREFMultirange Inputs, Serial 16-Bit ADCs_______________________________________________________________________________