Figure 11a. Timing Diagram Power-Down Modes, External Clock
Figure 11b. Timing Diagram Power-Down Modes, Internal Clock
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
______________________________________________________________________________________ 15
REFERENCE
BUFFER
REFERENCE-BUFFER
COMPENSATION
MODE
VREF
CAPACITOR
(µF)
POWER-DOWN
MODE
POWER-UP
DELAY
(µs)
MAXIMUM
SAMPLING RATE
(ksps)
Disabled — — Full 2 133
Enabled Internal — Fast 5 26
Enabled Internal — Full 300 26
Enabled External 4.7 Fast See Figure 13c 133
Enabled External 4.7 Full See Figure 13c 133
Disabled — — Fast 2 133
Table 4. Typical Power-Up Delay Times
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