
MAX1209
12-Bit, 80Msps, 3.3V IF-Sampling ADC
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3.3V, OV
DD
= 2.0V, GND = 0, REFIN = REFOUT (internal reference), V
IN
= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T = low, f
CLK
= 80MHz (50% duty cycle), T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Resistance R
CLK
Figure 5 5 kΩ
Input Capacitance C
CLK
2pF
DIGITAL INPUTS (CLKTYP, G/T, PD)
Input High Threshold V
IH
0.8 x
OV
DD
V
Input Low Threshold V
IL
0.2 x
OV
DD
V
V
IH
= OV
DD
±5
Input Leakage Current
V
IL
= 0 ±5
µA
Input Capacitance C
DIN
5pF
DIGITAL OUTPUTS (D11–D0, DAV, DOR)
D11–D0, DOR, I
SINK
= 200µA 0.2
Output Voltage Low V
OL
DAV, I
SINK
= 600µA 0.2
V
D11–D0, DOR, I
SOURCE
= 200µA
OV
DD
-
0.2
Output Voltage High V
OH
DAV, I
SOURCE
= 600µA
OV
DD
-
0.2
V
Tri-State Leakage Current I
LEAK
(Note 3) ±5 µA
D11–D0, DOR Tri-State Output
Capacitance
C
OUT
(Note 3) 3 pF
DAV Tri-State Output
Capacitance
C
DAV
(Note 3) 6 pF
POWER REQUIREMENTS
Analog Supply Voltage V
DD
3.0 3.3 3.6 V
Digital Output Supply Voltage OV
DD
1.7 2.0
V
DD
+
0.3V
V
Normal operating mode,
f
IN
= 175MHz at -0.5dBFS, CLKTYP = GND,
single-ended clock
111
Normal operating mode,
f
IN
= 175MHz at -0.5dBFS,
CLKTYP = OV
DD,
differential clock
119 132
Analog Supply Current I
VDD
Power-down mode clock idle, PD = OV
DD
0.001
mA
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