
Divide-by-1 mode See
Figures 2, 3
MAX101A
500Msps, 8-Bit ADC with Track/Hold
4 _______________________________________________________________________________________
DIV10 = 0, Figures 1 and 2
DIV10 = 0, Figures 1 and 2
ns
CLK, CLK
CLK, CLK
0.7 1.3 1.8t
PD2
DCLK to A/BData
Propagation Delay
DCLK
DATA
DCLK
DATA
20% to 80% ps
800
t
F
ns1.2 2.3 3.4t
PD1
CLK to DCLK
Propagation Delay
CONDITIONS
20% to 80%
300
Clock
Cycles
t
NPD
Divide-by-1 mode, Figures 2 and 3, Table 1Pipeline Delay (Latency) 15 15
ps
500
t
R
Fall Time
300
Rise Time
ns0.9 2.5t
PWH
ns0.9 2.5t
PWL
Clock Pulse Width Low
Clock Pulse Width High
UNITSMIN TYP MAXSYMBOLPARAMETER
TIMING CHARACTERISTICS
(V
EE
= -5.2V, V
CC
= +5V, R
L
= 100Ω to -2V, VA
RT
, VB
RT
= 0.95V, VA
RB
, VB
RB
= -0.95V, T
A
= +25°C, unless otherwise noted.)
Note 3: All devices are 100% production tested at +25°C and are guaranteed by design for T
A
= T
MIN
to T
MAX
as specified.
Note 4: Deviation from best-fit straight line. See
Integral Nonlinearity
section.
Note 5: See the
Signal-to-Noise Ratio and Effective Bits
section in the
Detailed Description of Specifications
.
Note 6: SNR calculated from effective bits performance using the following equation: SNR(dB) = 1.76 + 6.02 x effective bits.
Note 7: Clock pulse width minimum requirements t
PWL
and t
PWH
must be observed to achieve stated performance.
Note 8: Outputs terminated through 100Ω to -2.0V.
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
-0.75
0.75
0 256
-0.50
0.50
MAX101 TOC1
OUTPUT CODE
INL (LSBs)
64 192128
0
-0.25
0.25
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
-0.75
0.75
0 256
-0.50
0.50
MAX101 TOC2
OUTPUT CODE
DNL (LSBs)
64 192128
0
-0.25
0.25
__________________________________________Typical Operating Characteristics
(V
EE
= -5.2V, V
CC
= +5V, R
L
= 100Ω to -2V, VA
RT
, VB
RT
= 0.95V, VA
RB
, VB
RB
= -0.95V, T
A
= +25°C, unless otherwise noted.)
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