134
ATmega162/V
2513E–AVR–09/03
• Bit 5 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The
corresponding Interrupt Vector (See “Interrupts” on page 56.) is executed when the
OCF1B Flag, located in TIFR, is set.
• Bit 3 – TICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The
corresponding Interrupt Vector (See “Interrupts” on page 56.) is executed when the
ICF1 Flag, located in TIFR, is set.
Extended Timer/Counter
Interrupt Mask Register –
ETIMSK
(1)
Note: 1. This register contains interrupt control bits for several Timer/Counters, but only
Timer3 bits are described in this section. The remaining bits are described in their
respective Timer sections.
• Bit 5 – TICIE3: Timer/Counter3, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter3 Input Capture interrupt is enabled. The
corresponding Interrupt Vector (See “Interrupts” on page 56.) is executed when the
ICF3 Flag, located in TIFR, is set.
• Bit 4 – OCIE3A: Timer/Counter3, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter3 Output Compare A Match interrupt is enabled. The
corresponding Interrupt Vector (See “Interrupts” on page 56.) is executed when the
OCF3A Flag, located in TIFR, is set.
• Bit 3 – OCIE3B: Timer/Counter3, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter3 Output Compare B Match interrupt is enabled. The
corresponding Interrupt Vector (See “Interrupts” on page 56.) is executed when the
OCF3B Flag, located in TIFR, is set.
• Bit 2 – TOIE3: Timer/Counter3, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter3 overflow interrupt is enabled. The corresponding
Interrupt Vector (See “Interrupts” on page 56.) is executed when the TOV3 Flag, located
in TIFR, is set.
Bit 765 4 3 210
TICIE3 OCIE3A OCIE3B TOIE3 – –ETIMSK
Read/Write R R R/W R/W R/W R/W R R
Initial Value 0 0 0 0 0 0 0 0
(159 paginas)
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